Low threshold MOS two phase negative charge pump

A charge pump comprising:

• a first transistor having a gate, a first channel terminal coupled to a first node, and a second channel terminal coupled to its gate and a second node;
• a first capacitor having a first terminal coupled to the first node, and a second terminal adapted to receive a first clock signal;
• a second transistor having a gate, a first channel terminal coupled to a second node, and a second channel terminal coupled to its gate and to a third node;
• and
• a second capacitor having a first terminal coupled to the second node, and a second terminal adapted to receive a second clock signal;
• a third transistor having a gate, a first channel terminal coupled to the first node, and a second channel terminal coupled to a bias potential;
• wherein the first, second and third transistors respectively comprise a first region and a second region having a first conductivity type providing the first and second channel terminals respectively, a channel region in which the first and second regions are formed having a second conductivity type, the channel region being formed in an isolation well having the first conductivity type in a semiconductor substrate having the second conductivity type;
• the first and second regions, the channel region and the isolation well forming a parasitic bipolar junction transistor having a threshold voltage, and wherein the channel region has a doping concentration establishing a threshold voltage of the respective transistor less than the threshold voltage of the parasitic bipolar junction transistor.

An integrated circuit comprising:

• a semiconductor substrate;
• circuitry on the substrate adapted to operate in response to a operating voltage;
• a supply voltage terminal and a ground terminal on the substrate, adapted to receive a supply voltage within a prespecified range, the operating voltage outside of the prespecified range;
• and
• a charge pump coupled to the supply voltage terminal and the ground terminal including
• a clock circuit producing first and second clock signals;
• a first transistor having a gate, a first channel terminal coupled to a first node, and a second channel terminal coupled to its gate and a second node;
• a first capacitor having a first terminal coupled to the first node, and a second terminal adapted to receive a first clock signal;
• a second transistor having a gate, a first channel terminal coupled to a second node, and a second channel terminal coupled to its gate and to a third node;
• and
• a second capacitor having a first terminal coupled to the second node, and a second terminal adapted to receive a second clock signal;
• a third transistor having a gate, a first channel terminal coupled to the first node, and a second channel terminal coupled to a bias potential;
• wherein the first, second and third transistors respectively comprise a first region and a second region having a first conductivity type providing the first and second channel terminals respectively, a channel region in which the first and second regions are formed having a second conductivity type, the channel region being formed in an isolation well having the first conductivity type in a semiconductor substrate having the second conductivity type;
• the first and second regions, the channel region and the isolation well forming a parasitic bipolar junction transistor having a threshold voltage, and wherein the channel region has a doping concentration establishing a threshold voltage of the respective transistor less than the threshold voltage of the parasitic bipolar junction transistor.