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US 6,285,231 B1Granted
Reference buffer technique for high speed switched capacitor circuits
AssigneeNational Semiconductor Corporation
InventorsIon E. Opris, Laurence Douglas Lewicki
Life of this patent
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Abstract
A low power reference buffer includes a new amplifier design with very large transconductance and high frequency non-dominant poles and a triple bonding scheme to a large off-chip capacitor that avoids the problems related to the lead wire inductance.
Claims20
An apparatus including a reference buffer, comprising:
- a first amplifier having first and second input terminals and an output terminal, said first amplifier first input terminal configured to receive a first reference signal, said first amplifier including a voltage gain amplifier coupled to an adaptive biasing transconductance stage in series thereto;
- a second amplifier having a second amplifier first input terminal, a second amplifier second input terminal and a second amplifier output terminal;
- a common node;
- an output terminal;
- a first inductance coupled between said first amplifier output terminal and said common node;
- a second inductance coupled between said first amplifier second input and said common node;
- and
- a third inductance coupled to said common node and said output terminal;
- wherein said first inductance and said second inductance separate said first amplifier output terminal, and said first amplifier second input terminal, respectively, from said common node;
- wherein said second amplifier output terminal and said second amplifier second input terminal are coupled to said third inductance such that said second amplifier output terminal and second amplifier second input terminal are separated from said common node;
- and further
- wherein said second amplifier first input terminal is configured to receive a second reference signal.
9 more elements
A method of providing a reference buffer, comprising the steps of:
- providing a first amplifier having first and second input terminals and an output terminal, said first amplifier first input terminal configured to receive a first reference signal, said step of providing said first amplifier including the step of coupling a voltage gain amplifier to an adaptive biasing transconductance stage in series thereto;
- providing a second amplifier having a second amplifier first input terminal, a second amplifier second input terminal and a second amplifier output terminal;
- providing a common node;
- providing an output terminal;
- coupling a first inductance between said first amplifier output terminal and said common node;
- coupling a second inductance between said first amplifier second input and said common node;
- and
- coupling a third inductance to said common node and said output terminal;
- wherein said first inductance and said second inductance separate said first amplifier output terminal, and said first amplifier second input terminal, respectively, from said common node;
- wherein said second amplifier output terminal and said second amplifier second input terminal are coupled to said third inductance such that said second amplifier output terminal and second amplifier second input terminal are separated from said common node;
- and further
- wherein said second amplifier first input terminal is configured to receive a second reference signal.
9 more elements
Dependencies are inferred from the claim text.