Input buffer circuit with adjustable delay via an external power voltage
AssigneeHyundai Electronics Industries Co., Ltd.
InventorJoon-Ho Na
Life of this patent
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Abstract
An input buffer circuit compensates for a data hold time and reduces an operational current by implementing a delay operation with transistors having a long channel when the input buffer circuit is driven by a high external voltage. The input buffer circuit includes a delay unit to delay an input signal, the delay unit being powered by an external power voltage and having an associated variable delay which is varied according to a detection signal and the external power voltage, the detection signal indicating whether the external power voltage is high or low.
Claims19
An input buffer circuit comprising:
- a delay unit to delay an input signal, the delay unit being powered by an external power voltage and having an associated variable delay which is varied according to a detection signal and the external power voltage, the detection signal indicating whether the external power voltage is high or low, the delay unit including:
- a plurality of delay elements connected output-to-input so as to form a chain, each delay element having an individual variable delay which is varied according to a detection signal and the external power voltage.
A buffer circuit comprising:
- an external power detection unit for receiving an external voltage and generating a detecting signal;
- and
- a detection signal inverter for receiving the detection signal and generating an inverted detection signal;
- and
- a delay unit for delaying the input signal and receiving the detection signal and inverted detection signal, the delay unit including:
- a plurality of inverters connected in series, each inverter having a plurality of first transistors and a plurality of second transistors, each first transistor having channels configured with a first ratio of width to length and each second transistor having channels configured with a second ratio of width to length,
- wherein the first ratio is relatively larger than the second ratio and the differing ratios permit the buffer circuit to generate variable delays.
Dependencies are inferred from the claim text.