Integrated circuit for generating a phase-shifted output clock signal from a clock signal

An integrated circuit, comprising:

• an adjustable current source having a first output outputting a first adjustable current and a second output outputting a second adjustable current, wherein a sum of said first and second currents is substantially constant for different settings, and at least one control input for receiving a control signal for setting the first and second currents;
• a supply line for a first potential;
• a first transistor connected between said first output of said current source and said supply line for the first potential, said first transistor having a first channel terminal connected to said supply line and a second channel terminal remote therefrom, and a second transistor connected between said second output of said current source and said supply line for the first potential, said second transistor having a first channel terminal connected to said supply line and a second channel terminal remote therefrom;
• a circuit node and a precharge unit connected to said circuit node for precharging said circuit node to a second potential;
• a series circuit formed by a third transistor and a fourth transistor connected between said circuit node and said supply line;
• said third transistor having a control terminal connected to a first clock signal, said first transistor having a control terminal connected to said second channel terminal thereof, and said fourth transistor having a control terminal connected to said control terminal of said first transistor;
• a series circuit formed by a fifth transistor and a sixth transistor connected between said circuit node and said supply line;
• said fifth transistor having a control terminal connected to a second clock signal, phase-shifted relative to the first clock signal, said second transistor having a control terminal connected to said second channel terminal thereof, and said sixth transistor having a control terminal connected to said control terminal of said second transistor;
• and
• a level detector having an input connected to said circuit node and an output supplying an output clock signal at a first level when the potential at said circuit node lies below a lower switching threshold of said level detector, and at a second level when the potential at said circuit node lies above an upper switching threshold.