US 6,285,227 B1Granted

Latch ratio circuit with plural channels

AssigneeTexas Instruments Incorporated

InventorsHiroshi Takahashi, Yutaka Toyonoh, Yasumasa Ikezaki, Tohru Urasaki, Akihiro Takegama

Life of this patent

Estimating the term…

Loading patent…

Abstract

The purpose of this invention is to ensure an active use of the inverse short-channel effect in the ratio circuit and to guarantee stable operation at low power source voltage. In this ratio circuit, N-channel MOS transistor 12 of CMOS circuit 10 on one side forms the drive element, while P-channel MOS transistor 18 of CMOS circuit 16 on the other side forms the load element. Said N-channel MOS transistor 12 on the drive side and P-channel MOS transistor 16 on the load side have their drain terminals electrically connected to each other through transfer gate 22 made of N-channel MOS transistor. MOS transistor 12 on the drive side has a single channel CHa with the inverse short-channel effect. MOS transistor 18 on the load side has plural, e.g., two, channels CHb1 and CHb2, connected in tandem, each of which displays the inverse short-channel effect.

Claims8

Dependent claims

A latch circuit comprising:

a first MOS transistor of a first conductivity type which has a single channel with inverse short-channel effect and which has its source terminal connected to a first reference voltage terminal that supplies the first potential,
a transfer gate which has its input terminal connected to the drain terminal of said first MOS transistor,
a MOS transistive device of the second conductivity type which has plural tandem channels each having the inverse short-channel effect and connected in series, and which has its source terminal connected to a second reference voltage terminal that supplies a second potential different from said first potential and has its drain terminal connected to the output terminal of said transfer gate, and
an inverter, which has its input terminal connected to the drain terminal of said second MOS transistor and has its output terminal connected to the gate terminal of said second MOS transistor.

1 more element

Dependencies are inferred from the claim text.