Duty cycle correction circuit and method

A duty cycle correction circuit, comprising:

• an input clock terminal providing an unsymmetrical input clock signal having an input clock period and an input clock duty cycle;
• a delay line driven by the input clock signal and providing a plurality of intermediate clock signals delayed from the input clock signal by a plurality of unit delays;
• a multiplexer control circuit;
• a clock multiplexer selecting among the intermediate clock signals under control of the multiplexer control circuit to provide a selected clock signal, the selected clock signal being an intermediate clock signal subject to a delay closest to but not exceeding half of one input clock period;
• and
• an output clock generator driven by the selected clock signal and the input clock signal and providing an output clock signal having an output clock period the same as the input clock period and further having a 50% duty cycle,
• wherein the multiplexer control circuit comprises:
• a delay timer comprising a series of delay elements each having a delay equal to the unit delay of the delay line, the delay timer providing a series of bits indicative of the number of unit delays in one input clock period;
• and
• a decoder that receives the series of bits and provides therefrom a plurality of select signals for controlling the clock multiplexer.

A duty correction circuit, comprising:

• an input clock terminal providing an unsymmetrical input clock signal having an input clock period and an input clock duty cycle;
• a delay line driven by the input clock signal and providing a plurality of intermediate clock signals delayed from the input clock signal by a plurality of unit delays;
• a multiplexer control circuit;
• a clock multiplexer selecting among the intermediate clock signals under control of the multiplexer control circuit to provide a selected clock signal, the selected clock signal being an intermediate clock signal subject to a delay closest to but not exceeding half of one input clock period;
• and
• an output clock generator driven by the selected clock signal and the input clock signal and providing an output clock signal having an output clock period the same as the input clock period and further having a 50% duty cycle,
• wherein the delay line comprised a delay element selectably providing half of the unit delay, thereby delaying each of the plurality of intermediate clock signals by half of the unit delay.

A method of correcting the duty cycle of an input clock signal, the method comprising:

• receiving an unsymmetrical input clock signal having an input clock period and an input clock duty cycle;
• providing from the input clock signal a plurality of intermediate clock signals delayed form the input clock signals by a plurality of unit delays;
• selecting from among the intermediate clock signals a selected clock signal, the selection being made based on a number of unit delays in one input clock period, the selected clock signal being an intermediate clock signal subject to a delay closest to but not exceeding half off one input clock period;
• and
• providing from the selected clock signal and the input clock signal an output clock signal having an output clock period the same as the input clock period and further having a 50% duty cycle.

A method of correcting the duty cycle of an input clock signal, the method comprising:

• receiving an unsymmetrical input clock signal having an input clock period and an input clock duty cycle;
• providing from the input clock signal a plurality of intermediate clock signals delayed from the input clock signal by a plurality of unit delays;
• selecting from among the intermediate clock signals a selected clock signal, the selected clock signal being an intermediate clock signal subject to a delay closest to but not exceeding half of one input clock period;
• and
• providing from the selected clock signal and the input clock signal an output clock signal having an output clock period the same as the input clock period and further having a 50% duty cycle,
• wherein selecting from among the intermediate clock signals a selected clock signal comprises:
• counting a number of unit delays in one input clock period;
• and
• decoding the number of unit delays to select from among the intermediate clock signals the selected clock signal.

A method of correcting the duty cycle of an input clock signal, the method comprising:

• receiving an unsymmetrical input clock signal having an input clock period and an input clock duty cycle;
• providing from the input clock signal a plurality of intermediate clock signals delayed from the input clock signal by a plurality of unit delays;
• selecting from among the intermediate clock signals a selected clock signal, the selected clock signal being an intermediate clock signal subject to a delay closest to but not exceeding half of one input clock period;
• and
• providing from the selected clock signal and the input clock signal an output clock signal having an output clock period the same as the input clock period and further having a 50% duty cycle,
• wherein providing from the input clock signal a plurality of intermediate clock signals delayed from the input clock signal by a plurality of unit delays further comprises selectably delaying each of the plurality of intermediate clock signals by half of the unit delay.

A duty cycle correction circuit, comprising:

• means for receiving an unsymmetrical input clock signal having an input clock period and an input clock duty cycle;
• means for providing from the input clock signal a plurality of intermediate clock signals delayed from the input clock signal by a plurality of unit delays;
• means for selecting from among the intermediate clock signals a selected clock signal, the selection being made based on a number of unit delays in one input clock period, the selected clock signal being an intermediate clock signal subject to a delay closest to but not exceeding half of one input clock period;
• and
• means for providing from the selected clock signal and the input clock signal an output clock signal having an output clock period the same as the input clock period and further having a 50% duty cycle.

A duty cycle correction circuit, comprising:

• means for receiving an unsymmetrical input clock signal having an input clock period and an input clock duty cycle;
• means for providing from the input clock signal a plurality of intermediate clock signals delayed from the input clock signal by a plurality of unit delays;
• means for selecting from among the intermediate clock signals a selected clock signal, the selected clock signal being an intermediate clock signal subject to a delay closest to but not exceeding half of one input clock period;
• and
• means for providing from the selected clock signal and the input clock signal an output clock signal having an output clock period the same as the input clock period and further having a 50% duty cycle,
• wherein the means for selecting from among the intermediate clock signals a selected clock signal comprises:
• means for counting a number of unit delays in one input clock period;
• and
• means for decoding the number of unit delays to select from among the intermediate clock signals the selected clock signal.

A duty cycle correction circuit, comprising:

• means for receiving an unsymmetrical input clock signal having an input clock period and an input clock duty cycle;
• means for providing from the input clock signal a plurality of intermediate clock signals delayed from the input clock signal by a plurality of unit delays;
• means for selecting from among the intermediate clock signals a selected clock signal, the selected clock signal being an intermediate clock signal subject to a delay closest to but not exceeding half of one input clock period;
• and
• means for providing from the selected clock signal and the input clock signal an output clock signal having an output clock period the same as the input clock period and further having a 50% duty cycle,
• wherein the means for providing from the input clock signal a plurality of intermediate clock signals delayed from the input clock signal by a plurality of unit delays further comprises means for selectably delaying each of the plurality of intermediate clock signals by half of the unit delay.