Low frequency clock feed-through charge pump circuit

A low clock feed through charge pump circuit comprising:

• a first pump transistor having its own source electrically coupled to a power supply for serving as a current source;
• a second pump transistor having its own source electrically coupled to ground for serving as a current source;
• a first switch device having a first terminal electrically coupled to the drain of the first pump transistor, a second terminal, and a third terminal;
• a second switch device having a first terminal electrically coupled to the drain of the first pump transistor, a second terminal, and a third terminal electrically coupled to the third terminal of the first switch device;
• a third switch device having a first terminal electrically coupled to the second terminal of the first switch device, a second terminal electrically coupled to the drain of the second pump transistor, and a third terminal;
• a fourth switch device having a first terminal electrically coupled to the second terminal of the second switch device, a second terminal electrically coupled to the drain of the second pump transistor, and a third terminal electrically coupled to the third terminal of the third switch device;
• a first transistor having its gate and drain electrically coupled to the gate of the first pump transistor and the third terminal of the first switch device and its source electrically coupled to the power supply;
• a second transistor having its gate electrically coupled to the gate of the second pump transistor and the third terminal of the third switch device, its source electrically coupled to the ground, and its drain electrically coupled to the drain of the first transistor;
• and
• a third transistor having its gate and drain electrically coupled to the gate of the second transistor, its drain electrically coupled to an input current source, and its source electrically coupled to the ground.

A charge pump circuit applied in a phase locked loop circuit, comprising:

• a first pump transistor having its own source electrically coupled to a power supply for serving as a current source;
• a second pump transistor having its own source electrically coupled to ground for serving as a current source;
• a first switch device having a first terminal electrically coupled to the drain of the first pump transistor, a second terminal, and a third terminal;
• a second switch device having a first terminal electrically coupled to the drain of the first pump transistor, a second terminal, and a third terminal electrically coupled to the third terminal of the first switch device;
• a third switch device having a first terminal electrically coupled to the second terminal of the first switch device, a second terminal electrically coupled to the drain of the second pump transistor, and a third terminal;
• a fourth switch device having a first terminal electrically coupled to the second terminal of the second switch device, a second terminal electrically coupled to the drain of the second pump transistor, and a third terminal electrically coupled to the third terminal of the third switch device;
• a first cascode transistor circuit electrically coupled between the power supply and ground and consisting of at least a first transistor and a second transistor, wherein the first transistor of the first cascode transistor circuit has its own gate electrically coupled to the third terminal of the first switch device, and the second transistor of the first cascode transistor circuit has its own gate electrically coupled to the gate of the first pump transistor, and the drain of the first transistor;
• a second cascode transistor circuit consisting of a first transistor and a second transistor and having the gate of the first transistor of the second cascode transistor circuit electrically coupled to the third terminal of the fourth switch device, the gate of the second transistor of the second cascode transistor circuit electrically coupled to the gate of the second pump transistor, and the drain of the first transistor and the drain of the first transistor of the second cascode transistor circuit electrically coupled to an input circuit source for providing an input current of the low clock feed through charge pump circuit;
• wherein the first and fourth switch devices each further has:
• a switch transistor electrically coupled to the first pump transistor and operating in a saturation region;
• a first control transistor electrically coupled between the power supply and the gate of the switch transistor, and operating at a linear region;
• and
• a second control transistor electrically coupled between the third terminal and the gate of the switch transistor, and operating at a linear region.