Method and apparatus for implementing logic using mask-programmable dynamic logic gates
AssigneeInternational Business Machines Corporation
InventorsSang Hoo Dhong, Hung Cai Ngo, Jaehong Park, Osamu Takahashi
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Abstract
A method and apparatus for implementing dynamic logic with programmable dynamic logic gates acts as a complement to programmable logic arrays (PLAs) used in high-speed microprocessor designs. A matrix of selectable cells provides powerful logic functions such as AND-OR gate capability with a minimum of inputs and transistors. By using programmable logic arrays and programmable dynamic gates, the efficiency of a logic block can be dramatically improved with little added circuit area.
Claims20
A dynamic programmable logic gate having a plurality of logic inputs, said dynamic programmable logic gate comprising:
- a precharge device for precharging a summing node of said dynamic programmable logic gate;
- and
- a cell matrix coupled to said summing node, wherein said cell matrix includes a predetermined number of cells, wherein each of said cells includes a semiconductor device including a channel and a gate, wherein each of said cells can be activated for use in said dynamic programmable logic gate by depositing a metal contact to form either a conductor cell or a transistor cell.
A method for fabricating programmable logic using a dynamic programmable logic gate having a plurality of logic inputs, a summing node, and a cell matrix coupled to said summing node, wherein said cell matrix includes semiconductor devices distributed in cells forming rows and columns, wherein said cells are adapted for accepting metal contacts forming one of a conductor cell or a transistor cell, and wherein said method comprises the steps of:
- determining whether or not a logic cell is required at a location within said cell matrix;
- responsive to determining said logic cell is required, second determining whether or not said logic cell is a conductor cell or a transistor cell;
- responsive to determining said logic cell is a conductor cell, depositing a shunt conductor to short a channel of a semiconductor device distributed in said location;
- and
- responsive to determining said logic cell is a transistor cell, depositing a gate conductor to couple a gate of said semiconductor device distributed in said location to one of said plurality of logic inputs.
A method of operating programmable logic using a dynamic programmable logic gate having a plurality of logic inputs and a summing node, wherein said method comprises the steps of:
- precharging said summing node;
- and
- discharging said summing node through a cell matrix coupled to said summing node, wherein said cell matrix includes semiconductor devices distributed in cells forming rows and columns, wherein said cells are adapted for accepting metal contacts forming one of a conductor cell or a transistor cell, and wherein said transistor cell has a gate coupled to one of said plurality of logic inputs.
Dependencies are inferred from the claim text.