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US 6,285,217 B1Granted
Dynamic logic circuits with reduced evaluation time
AssigneeInternational Business Machines Corporation
InventorsChristopher McCall Durham, Peter Juergen Klim, Younes Lofti, John Beck
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Abstract
Dynamic logic circuits with reduced evaluation time provide faster output in dynamically evaluating logic circuits by increasing the rate of change of the voltage at the junction of logic input ladders. The circuits use a cross-coupled amplifier to charge the input ladder combining node once the node begins to evaluate.
Claims12
A dynamic logic gate comprising:
- at least one input ladder that evaluates a combination of logic signals by discharging a precharge potential at a logical evaluation node during an evaluation phase;
- a cross-coupled amplifier that provides a parallel discharge path from said logical evaluation node, wherein said cross-coupled amplifier includes:
- a first input terminal coupled to said logical evaluation node;
- and
- a second input terminal;
- switching means for shunting said first input terminal with said second input terminal during a precharge phase and for opening said shunt during an evaluation phase;
- and
- switching means for selectively delaying application of said parallel discharge path to said logical evaluation node until after an evaluation phase has begun.
5 more elements
A method for utilizing a cross-coupled amplifier to reduce the evaluation time of a dynamic circuit, said method comprising:
- utilizing a cross-coupled amplifier to sense the direction of change of a voltage at a logical evaluation node;
- and
- detecting that a voltage of said logical evaluation node is evaluating to a non-precharge state, and in response thereto, applying an additional discharge path from said evaluation node through said cross-coupled amplifier.
Dependencies are inferred from the claim text.