High speed output enable path and method for an integrated circuit device
AssigneeUnited Microelectronics Corp.
InventorsJon Allan Faue, Harold Brett Meadows
Life of this patent
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Abstract
A high speed output enable path and method for an integrated circuit device which effectively minimizes the gate delays in the critical integrated circuit device data and clock paths and in which most amplification is added in the reset path which is not critical to access time. Based on an external clock, several “one-shot” internal output enable clocks are generated. These parallel output enable clocks have select information embedded in them to facilitate the multiplexing of several different data paths onto a single output buffer. This select information is implemented ir the reset portion of the one-shot circuit thereby removing it from the critical portion for determining access time.
Claims28
An output enable circuit for an integrated circuit device, said circuit comprising:
- a clock buffer for receiving an external clock signal and producing an internal clock signal displaced from said external clock signal by a delay imposed by said clock buffer circuit;
- a reset circuit coupled to said clock buffer circuit for producing a reset clock signal displaced from said internal clock signal by a delay imposed by said reset circuit;
- at least one output enable logic circuit coupled to receive said internal clock signal and said reset clock signal, said output enable logic circuit producing an output enable clock signal having a first state thereof initiated on a first logic level transition of said internal clock signal and a second state thereof initiated on an opposite second logic level transition of said reset clock signal;
- and
- at least one pass gate coupled to receive said output enable clock signal and a data signal, said pass gate operative to provide said data signal to an output node when said output enable clock signal is in said first state thereof.
A process for multiplexing data from multiple data sources to a common output node on an integrated circuit device, said process comprising:
- supplying an external clock signal to said integrated circuit device;
- buffering said external clock signal to provide an internal clock signal having n gate delays;
- delaying said internal clock signal to provide a reset clock signal having an odd number of additional gate delays;
- producing at least one output enable clock signal having a first state thereof initiated on a first logic level transition of said internal clock signal and a second state thereof initiated on an opposite second logic level transition of said reset clock signal;
- and
- passing data corresponding to one of said data sources to said common output node in response to said output enable clock signal being in said first state thereof.
Dependencies are inferred from the claim text.