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AssigneesAltera Corporation, Quickturn Design Systems, Inc.
InventorsStephen P. Sample, Michael R. Butts, Kevin A. Norman, Rakesh H. Patel
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An integrated circuit for implementing reconfigurable logic, such as a field programmable gate array (“FPGA”), as described herein has flexible input/output buffer circuits. These input/output buffer circuits transfer data either bidirectionally or unidirectionally between an input/output pin and a FPGA core. Each input/output buffer circuit allows at least two signals to be time-multiplexed onto an input/output pin thereby doubling the effective input/output capacity. The input/output buffer circuits may be used to time-multiplex at least two signals onto an input pin, at least two signals onto an output pin, or both. Each input/output buffer circuit further has shared flip flops for time-multiplexing signals. The circuitry provides two connections into the FPGA core which can be used to time-multiplex at least two independent inputs or outputs.
An integrated circuit comprising:
A circuit for implementing re-configurable logic, comprising:
An integrated device for implementing re-configurable logic, comprising:
The integrated device of 3 wherein the first input/output buffer is configured to transmit the first signal from the first connection to the input/output pin along a first path, and to transmit the second signal from the second connection to the input/output pin along a second path, wherein the first and second paths are substantially independent of each other.
The integrated device of 3 wherein the first input/output buffer is capable of receiving a third signal and a fourth signal via the input/output pin in a time-multiplexed manner, transmitting the third signal to the core via the first connection, and transmitting the fourth signal to the core via the second connection.
The integrated device of 5 wherein the first input/output buffer is configured to transmit the third signal to the first connection along a third path, and to transmit the fourth signal to the second connection along a fourth path, wherein the third and fourth paths are substantially independent of each other.
The integrated device of 5 wherein the first input/output buffer is capable of transmitting the third and fourth signals to the core after a programmable delay.
The integrated device of 5 wherein the first input/output buffer further comprises:
The integrated device of 8 wherein the first input/output buffer further comprises:
The integrated device of 3 further comprising:
The integrated device of 10 wherein a signal received from the core via the third connection is used to control a mode of operation of the first input/output buffer.
The integrated device of 3 wherein the first input/output buffer is capable of time-multiplexing the first and second signals asynchronously relative to tirnings of the first and second signals.
A circuit for implementing reconfigurable logic, comprising:
In an integrated circuit device comprising a core, an input/output buffer, and an input/output pin, a method of communicating signals between the core and the input/output pin, the method comprising:
In an integrated circuit device comprising a core, an input/output buffer, and an input/output pin, a method of communicating signals between the core and the input/output pin, the method comprising:
Dependencies are inferred from the claim text.