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US 6,285,208 B1Granted
Activation speed of signal wiring line in semiconductor integrated circuit
AssigneeNEC Corporation
InventorMiyoshi Ohkubo
Life of this patent
Estimating the term…
Abstract
A semiconductor integrated circuit includes a plurality of signal wiring lines, and a plurality of shield wiring lines, each of which is arranged between adjacent two of the plurality of signal wiring lines. An interference preventing section is connected to the plurality of shield wiring lines, and supplies an inference preventing signal to two of the plurality of shield wiring lines adjacent to a specific one of the plurality of signal wiring lines. The inference preventing signal is switched to have a same phase as an input signal which is supplied to the specific signal wiring line.
Claims19
A semiconductor integrated circuit comprising:
- a plurality of signal wiring lines;
- a plurality of shield wiring lines, each of which is arranged between adjacent two of said plurality of signal wiring lines;
- an interference preventing section connected to said plurality of shield wiring lines, for supplying to two of said plurality of shield wiring lines adjacent to a specific one of said plurality of signal wiring lines, an interference preventing signal which is switched to have a same phase as an input signal which is supplied to said specific signal wiring line, wherein said interference preventing section includes a plurality of interference preventing circuits, each of said plurality of interference preventing circuits including a gate circuit having two input terminals that receive input from two of said plurality of siganl wiring lines adjacent to said shield wiring line corresponding to said each interference preventing circuit and provides output to said shield wiring line, wherein said gate circuit includes at least one of:
- a NAND gate, a NOR gate, and an exclusive OR gate.
1 more element
A semiconductor integrated circuit comprising:
- a plurality of signal wiring lines;
- a plurality of shield wiring lines, each of which is arranged between adjacent two of said plurality of signal wiring lines;
- an interference preventing section connected to said plurality of shield wiring lines, for supplying to two of said plurality of shield wiring lines adjacent to a specific one of said plurality of signal wiring lines, an interference preventing signal which is switched to have a same phase as an input signal which is supplied to said specific signal wiring line,
- wherein a plurality of said input signals are supplied to said plurality of signal wiring lines, and only one of said plurality of input signals is switched when said plurality of input signals are switched, wherein said interference preventing section includes a plurality of interference preventing circuits, each of said plurality of interference preventing circuits including a gate circuit having two input terminals that receive input from two of said plurality of signal wiring lines adjacent to said shield wiring line corresponding to said each interference preventing circuit and provides output to said shield wiring line, wherein said gate circuit includes at least one of:
- a NAND gate, a NOR gate, and an exclusive OR gate.
2 more elements
A semiconductor integrated circuit comprising:
- a plurality of signal wiring lines;
- a plurality of shield wiring lines, each of which is arranged between adjacent two of said plurality of signal wiring lines;
- an interference preventing section connected to said plurality of shield wiring lines, for supplying to two of said plurality of shield wiring lines adjacent to a specific one of said plurality of signal wiring lines, an interference preventing signal which is switched to have a same phase as an input signal which is supplied to said specific signal wiring line,
- wherein said interference preventing section includes a plurality of interference preventing circuits respectively connected to said shield wiring lines, and
- wherein each of said plurality of interference preventing circuits includes a NAND gate circuit, which has two input terminals are connected to inverted signals of said input signals to two of said plurality of signal wiring lines adjacent to said shield wiring line corresponding to said interference preventing circuit, and which has an output terminal connected to said corresponding shield wiring line.
2 more elements
A semiconductor integrated circuit comprising:
- a plurality of signal wiring lines;
- a plurality of shield wiring lines, each of which is arranged between adjacent two of said plurality of signal wiring lines;
- an interference preventing section connected to said plurality of shield wiring lines, for supplying to two of said plurality of shield wiring lines adjacent to a specific one of said plurality of signal wiring lines, an interference preventing signal which is switched to have a same phase as an input signal which is supplied to said specific signal wiring line,
- wherein said interference preventing section includes a plurality of interference preventing circuits respectively connected to said shield wiring lines, and,
- wherein each of said plurality of interference preventing circuits includes:
- a NOR gate circuit, which has two input terminals are connected to two of said plurality of signal wiring lines adjacent to said shield wiring line corresponding to said interference preventing circuit;
- and
- an inverter connected to an output terminal of said NOR gate circuit and connected to said corresponding shield wiring line.
5 more elements
A semiconductor integrated circuit, comprising,
- a plurality of signal wiring lines;
- a plurality of shield wiring lines, each of which is arranged between adjacent two of said plurality of signal wiring lines;
- an interference preventing section connected to said plurality of shield wiring lines, for supplying to two of said plurality of shield wiring lines adjacent to a specific one of said plurality of signal wiring lines, an interference preventing signal which is switched to have a same phase as an input signal which is supplied to said specific signal wiring line,
- wherein said interference preventing section includes a plurality of interference preventing circuits respectively connected to said shield wiring lines, and
- wherein each of said plurality of interference preventing circuits includes an exclusive OR gate circuit, which has two input terminals are connected to inverted signals of said input signals to two of said plurality of signal wiring lines adjacent to said shield wiring line corresponding to said interference preventing circuit, and which has an output terminal connected to said corresponding shield wiring line.
2 more elements
A semiconductor integrated circuit comprising:
- a plurality of signal wiring lines;
- a plurality of shield wiring lines, each of which is arranged between adjacent two of said plurality of signal wiring lines;
- an interference preventing section connected to said plurality of shield wiring lines, for supplying to two of said plurality of shield wiring lines adjacent to a specific one of said plurality of signal wiring lines, an interference preventing signal which is switched to have a same phase as an input signal which is supplied to said specific signal wiling line,
- wherein said plurality of signal wiring lines and said plurality of shield wiring lines are provided in an insulating film formed on a semiconductor substrate, and wherein each of said plurality of signal wiring lines is shielded by adjacent one or two of said plurality of shield wiring lines on one side or both sides of said signal wiring line, wherein said interference preventing section includes a plurality of interference preventing circuits, each of said plurality of interference preventing circuits including a gate circuit having two input terminals that receive input from two of said plurality of signal wiring lines adjacent to said shield wiring line corresponding to said each interference preventing circuit and provides output to said shield wiring line, wherein said gate circuit includes at least one of:
- a NAND gate, a NOR gate, and an exclusive OR gate.
2 more elements
A method of increasing an activation speed of a signal wiring line in a semiconductor integrated circuit, comprising the steps of:
- providing a plurality of signal wiring lines
- providing a plurality of shield wiring lines;
- and
- shielding a specific one of said plurality of signal wiring lines from other of said plurality of signal wiring lines by first and second of said plurality of shield wiring lines which are provided to sandwich said specific one signal wiring line without being connecting to predetermined potentials, when a plurality of input signals are supplied to said plurality of signal wiring lines such that only said specific one signal wiring line of said plurality of signal wiring lines is activated;
- connecting an interference preventing section to said plurality of shield wiring lines, for supplying to two of said plurality of shield wiring lines adjacent to a specific one of said plurality of signal wiring lines, an interference preventing signal which is switched to have a same phase as an input signal which is supplied to said specific signal wiring line, wherein said interference preventing section includes a plurality of interference preventing circuits, each of said plurality of interference preventing circuits including a gate circuit having two input terminals that receive input from two of said plurality of signal wiring lines adjacent to said shield wiring line corresponding to said each interference preventing circuit and provides output to said shield wiring line, wherein said gate circuit includes at least one of:
- a NAND gate, a NOR gate, and an exclusive OR gate.
3 more elements
A method of increasing an activation speed of a signal wiring line in a semiconductor integrated circuit, comprising the steps of:
- providing a plurality of signal wiring lines;
- providing a plurality of shield wiring lines;
- shielding a specific one of said plurality of signal wiring lines from other of said plurality of signal wiring lines by first and second of said plurality shield wiring lines which are provided to sandwich said specific signal wiring line without being connecting to predetermined potentials, when a plurality of input signals are supplied to said plurality of signal wiring lines such that only said specific signal wiring line of said plurality of signal wiring lines is activated,
- wherein said shielding step further includes shielding said specific signal wiring line from a semiconductor substrate;
- and
- connecting an interference preventing section to said plurality of shield wiring lines, for supplying to two of said plurality of shield wiring lines adjacent to a specific one of said plurality of signal wiring lines, an interference preventing signal which is switched to have the same phase as an input signal which is supplied to a specific signal wiring line, wherein said interference preventing section includes a plurality of interference preventing circuits, each of said plurality of interference preventing circuits including a gate circuit having two input terminals that receive input from two of said plurality of signal wiring lines adjacent to said shield wiring line corresponding to said each interference preventing circuit and provides output to said shield wiring line, wherein said gate circuit includes at least one of:
- a NAND gate, a NOR gate, and an exclusive OR gate.
4 more elements
Dependencies are inferred from the claim text.