Test system having alignment member for aligning semiconductor components

A test system for testing a semiconductor component having a plurality of component contacts comprising:

• a substrate having a thickness;
• an alignment member configured to align the component on the substrate, the alignment member comprising a pocket in the substrate having a depth that is less than the thickness, the pocket comprising a surface at the depth and a sidewall enclosing the surface configured to engage an edge of the component;
• and
• a plurality of contacts on the surface configured to electrically engage the component contacts.

A test system for testing a semiconductor component having a plurality of component contacts comprising:

• a substrate;
• an alignment member configured to align the component on the substrate, the alignment member comprising a sloped sidewall comprising a first etched portion of the substrate configured to engage an edge of the component, and a surface comprising a second etched portion of the substrate enclosed by the sloped sidewall;
• and
• a plurality of contacts on the surface configured to electrically engage the component contacts as the sloped sidewall engages the edge of the component.

A test system for testing a semiconductor component having bumped contacts comprising:

• a base configured to retain the component;
• an interconnect on the base comprising a substrate and a plurality of contacts on the substrate comprising projections configured to electrically engage the bumped contacts, and recesses configured to center the bumped contacts on the projections;
• and
• an alignment member comprising a pocket extending part way through the substrate having a sidewall with a peripheral outline corresponding to a peripheral edge of the component, and a surface enclosed by the sidewall,
• the contacts located on the surface,
• the sidewall configured to engage the peripheral edge of the component to align the bumped contacts to the contacts.

A method for fabricating a test system for testing a semiconductor component having a plurality of component contacts comprising:

• providing a substrate;
• forming an alignment member on the substrate by etching a pocket in the substrate comprising a surface and a sidewall enclosing the surface and configured to contact an edge of the component to align the component on the substrate;
• and
• forming a plurality of contacts on the surface configured to electrically engage the component contacts as the sidewall engages the edge.

A method for fabricating a test system for testing a semiconductor component having a plurality of component contacts comprising:

• providing a substrate having a thickness;
• forming an alignment member integrally with the substrate by etching a pocket in the substrate having a depth less than the thickness, the pocket comprising a surface comprising a first etched portion of the substrate and a sidewall comprising a second etched portion of the substrate extending to and enclosing the surface, the sidewall configured to contact an edge of the component to align the component on the substrate;
• and
• forming a plurality of contacts on the surface configured to electrically engage the component contacts.