System and method for generating a jittered test signal
AssigneePhilips Electronics North America Corporation
InventorMarc S. Walker
Life of this patent
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Abstract
A jitter unit converts a stable input test signal into a jittering output test signal used to test the jitter tolerance of electronic equipment. This jitter device allows any test or sample signal (analog or digital, video or audio) to be used for testing such equipment. Jitter is a type of timing error between the expected or ideal timing of a signal and the actual timing of a signal in which the characteristics of the timing error change with time. The characteristics of jitter include the level of error, the frequency of change in the error and whether the change is periodic or random. The jitter unit uses a variable delay unit to delay the signal and uses a controller to regulate the delay of the delay unit in order to transform the stable signal into a jittering signal.
Claims7
A system for producing a jittering test signal, comprising:
- means for delaying a signal with means to vary the delay depending on a jitter control signal;
- an input for a substantially non-jittering test signal to the signal delay means;
- an output for the delayed signal from the signal delay means;
- an input for the delay control signal;
- and
- means for providing a jitter control signal to the delay control signal input in order to provide jittering of the test signal.
A system for testing at least portions of electronic equipment, comprising
- means for providing a substantially non-jittering test signal;
- means for providing a jitter control signal;
- and
- means for delaying the test signal by a variable amount depending on the jitter control signal to provide a jittering test signal.
A method for generating a jittering test signal, which comprises:
- generating a substantially non-jittering test signal;
- generating a jitter control signal;
- providing said test signal to a signal input of a variable delay circuit;
- and
- providing said jitter control signal to a control input of said variable delay circuit to generate the jittering test signal at an output of said variable delay circuit.
Dependencies are inferred from the claim text.