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US 6,285,173 B1Granted
Method to switch MOSFETs using recycled, parasitic energy
AssigneeTexas Instruments Incorporated
InventorsAriel S. Bentolila, Sisan Shen
Life of this patent
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Abstract
An energy efficient gate drive technique for binary push-pull MOSFET switching systems having a common switch node with inductive and capacitive elements connected to this common switch node. These energy storage elements on the common switch node can be parasitic in nature or discrete components. This technique recycles otherwise lost PMOS gate drive energy through the switch node, as a storage element, to the NMOS output FET.
Claims15
A MOSFET switching system comprising:
- at least one NMOS FET;
- at least one PMOS FET connected to the at least one NMOS FET to formulate a totem-pole, binary push-pull, configuration having a common switch node;
- at least one energy storage element connected to the common switch mode;
- and
- a gate drive system connected to the common switch node and configured such that the gate drive system in association with the at least one energy storage element can supply and store gate energy for the at least one PMOS FET and the at least one NMOS FET in response to gate control signals, wherein at least some of the gate energy is provided by the energy storage element.
2 more elements
A MOSFET switching system comprising:
- at least one NMOS FET having a gate, drain and source;
- at least one PMOS FET having a gate, drain and source and connected to the at least one NMOS FET to formulate a totem-pole, binary push-pull, configuration having a common switch node;
- at least one energy storage element connected to the common switch node;
- a first switch connected at one end to the PMOS FET gate and connected at an opposite end to a switching system ground;
- a second switch connected at one end to the NMOS FET gate and connected at an opposite end to a switching system supply voltage;
- a third switch connected at one end to the PMOS FET gate and coupled at an opposite end to the common switch node;
- a fourth switch coupled at one end to the NMOS FET gate and connected at an opposite end to the common switch node;
- a first delay element connected at one end to the first switch and connected at an opposite end to the third switch;
- and
- a second delay element connected at one end to the second switch and connected at an opposite end to the fourth switch.
7 more elements
Dependencies are inferred from the claim text.