Digital phase-locked loop circuit with reduced phase jitter frequency

A method for generating a chip clock in a substantially constant phase relationship relative to a system clock, comprising the steps of:

• receiving a system clock;
• applying the system clock to a first digital delay line to generate a first delayed clock;
• distributing at least one clock signal based upon the first delayed clock to a circuit function;
• generating a feedback clock by applying the first delayed clock to a second digital delay line;
• monitoring the phase relationship of corresponding edges of the system clock and the feedback clock;
• responsive to the monitoring step detecting that corresponding edges of the system clock and the feedback clock differ in time by more than a selected threshold, generating a direction signal having a state indicating which of the system clock and feedback clock leads the other;
• then storing a state of the direction signal for later use;
• comparing the stored state of the direction signal with a current state of the direction signal;
• responsive to the comparing step indicating that the stored direction signal matches the current state of the direction signal, incrementally varying the delay length of the first digital delay line in a direction corresponding to the current state of the direction signal;
• and
• responsive to the comparing step indicating that the stored direction signal does not match the current state of the direction signal, incrementally varying the delay length of the second digital delay line in a direction corresponding to the current state of the direction signal.

An integrated circuit, comprising:

• a logic function, having a clock input;
• and
• a digital phase-locked loop, comprising:
• a phase detector, having a first input for receiving a system clock and a second input for receiving a feedback clock, for generating a shift signal at a shift clock output responsive to a detecting a phase difference between the system and feedback clocks, and for generating a direction signal at a direction output indicating which of the system and feedback clocks leads the other;
• a latch, for storing the state of the direction signal;
• an exclusive-OR function, having a first input coupled to the output of the latch and a second input coupled to receive the direction signal from the phase detector, for comparing the contents of the latch corresponding to a stored state of the direction signal with the current state of the direction signal;
• a first digital delay line, having an input coupled to receive the system clock, for generating a first delayed clock from the system clock, the first digital delay line having a direction input coupled to the direction output of the phase detector, and having a shift clock input, the first digital delay line having a delay length that is selectively incremented or decremented according to a signal at its direction input, responsive to receiving a shift signal at the shift clock input;
• a first gate, having a first input coupled to the output of the exclusive-OR function and having a second input coupled to the shift clock output of the phase detector, for blocking shift signals from being applied to the shift clock input of the first digital delay line responsive to the exclusive-OR function determining that the contents of the latch differ from the current state of the direction signal;
• a second digital delay line, having an input coupled to receive the first delayed clock, for generating the feedback clock therefrom, the first digital delay line having a direction input coupled to the direction output of the phase detector, and having a shift clock input, the second digital delay line having a delay length that is selectively incremented or decremented according to a signal at its direction input, responsive to receiving a shift signal at the shift clock input;
• and
• clock distribution circuitry, for receiving the first delayed clock and for applying, to the clock input of the logic function, a chip clock based upon the first delayed clock.

An electronic system, comprising:

• a clock generator circuit for generating a system clock;
• a plurality of integrated circuits, at least one of the plurality of integrated circuits comprising:
• a logic function, having a clock input;
• and
• a digital phase-locked loop, comprising:
• a phase detector, having a first input for receiving the system clock and a second input for receiving a feedback clock, for generating a shift signal at a shift clock output responsive to detecting a phase difference between the system and feedback clocks, and for generating a direction signal at a direction output indicating which of the system and feedback clocks leads the other;
• a latch, for storing the state of the direction signal;
• an exclusive-OR function, having a first input coupled to the output of the latch and a second input coupled to receive the direction signal from the phase detector, for comparing the contents of the latch corresponding to a stored state of the direction signal with the current state of the direction signal;
• a first digital delay line, having an input coupled to receive the system clock, for generating a first delayed clock from the system clock, the first digital delay line having a direction input coupled to the direction output of the phase detector, and having a shift clock input, the first digital delay line having a delay length that is selectively incremented or decremented according to a signal at its direction input, responsive to receiving a shift signal at the shift clock input;
• a first gate, having a first input coupled to the output of the exclusive-OR function and having a second input coupled to the shift clock output of the phase detector, for blocking shift signals from being applied to the shift clock input of the first digital delay line responsive to the exclusive-OR function determining that the contents of the latch differ from the current state of the direction signal;
• a second digital delay line, having an input coupled to receive the first delayed clock, for generating the feedback clock therefrom, the first digital delay line having a direction input coupled to the direction output of the phase detector, and having a shift clock input, the second digital delay line having a delay length that is selectively incremented or decremented according to a signal at its direction input, responsive to receiving a shift signal at the shift clock input;
• and
• clock distribution circuitry, for receiving the first delayed clock and for applying, to the clock input of the logic function, a chip clock based upon the first delayed clock.