Semiconductor device employing grid array electrodes and compact chip-size package

Abstract

There is described a plastic molding semiconductor package employing a ball grid array (BGA) and a compact chip-size package (CSP) in combination which can alleviate the stress exerted on electrode bumps, can reduce noise and cross-talk among signal electrodes, can increase a coefficient of thermal expansion, and can prevent passage of neutrons. A semiconductor chip is stacked on an insulating substrate by way of a stress alleviation film. The stress alleviation film is bonded to a marginal area of the semiconductor chip which has the maximum stress distribution density stemming from a difference in coefficient of thermal expansion between the semiconductor chip and the insulating substrate, and shielding electrodes are provided in the marginal area of the insulating substrate. As a result, the stress exerted on the semiconductor chip and the signal electrodes is alleviated. The stress alleviation film having a shielding layer is bonded to the marginal area of the semiconductor chip. Each of the signal electrodes provided on the insulating substrate may be coaxially surrounded by a cylindrical shielding array. A package having a heat sink maybe used for packaging the semiconductor device. Any one of the insulating substrate, a sealing material, and the package may be formed from deuterium-containing resin.

Dependencies are inferred from the claim text.