US 6,285,074 B1Granted

Semiconductor device

AssigneesHitachi, Ltd., Hitachi ULSI Systems Co., Ltd.

InventorsMichiaki Sugiyama, Tamaki Wada, Masachika Masuda

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Abstract

In a package of an LOC (Lead On Chip) structure in which inner lead portions are partially arranged over a major face of a semiconductor chip, there is disclosed a technique for thinning the package and speeding up signal transmission. Specifically, by partially reducing the thicknesses of the signal inner leads arranged over the major face of the semiconductor chip, the thickness of a sealing resin is reduced while ensuring the mechanical strength of the package. Moreover, the signal inner leads arranged over the major face of the semiconductor chip are arranged at predetermined spacings from the major face of the semiconductor chip. The power supplying inner leads are bonded to the major face of the semiconductor chip, thus providing a package having a reduced parasitic capacitance.

Claims9

Dependent claims

A semiconductor device comprising:

a semiconductor chip including an integrated circuit and external terminals formed in a major surface thereof;
a first lead and a second lead, each having an inner lead and an outer lead which is formed integrally with said inner lead, said inner lead of each of said first and second leads having a first portion which extends on said major surface of said semiconductor chip and a second portion which is outside of said semiconductor chip;
bonding wires electrically connecting said inner leads of said first and second leads with the corresponding external terminals of said external terminals, respectively;
and
a resin member sealing said semiconductor chip, said inner leads of said first and second leads and said bonding wires,
wherein a thickness of said first portion of each of said first and second leads is thinner than a thickness of said second portion of each of said first and second leads in a thickness direction of said semiconductor chip,
wherein said first portion of said first lead is spaced from said major surface of said semiconductor chip in said thickness direction of said semiconductor chip, and
wherein said first portion of said second lead is bonded to said major surface of said semiconductor chip by an adhesive layer formed between said first portion of said second lead and said major surface of said semiconductor chip.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 09/761,572Filed 18 Jan 2001 · continuation
Priority: JP 9-22799525 Aug 1997
Published: US 2001/0001504 A124 May 2001
Granted: 4 Sep 2001
Term ends: Not estimatedThe source records don’t support an estimate.

Classification22 codes

H10W 70/415
Chip-supporting parts, e.g. die pads: leadframe inner leads serving as die pads
H10W 72/07532
Techniques: compression bonding, e.g. thermocompression bonding
H10W 72/07533
Compression bonding, e.g. thermocompression bonding: ultrasonic bonding, e.g. thermosonic bonding
H10W 72/522
Structures or relative sizes of bond wires: multilayered bond wires, e.g. having a coating concentric around a core

Family

Application09/139,563Parent of this continuation · filed 25 Aug 1999
Application09/563,756Parent of this continuation · filed 1 May 2000
US 6,153,922 AParent of this continuation
US 2001/0001504 A1Published application
US 6,297,545 B1Related patent
US 6,285,074 B1This patent

From the US filing history. Foreign family members aren’t listed.