Structure and method for fabricating a field effect transistor with a self-aligned anti-punchthrough implant channel
AssigneeUnited Microelectronics Corp.
InventorsYau-Kae Shell, Gary Hong
Life of this patent
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Abstract
A structure and method for fabricating a field effect transistor (FET) having improved drain to source punchthrough properties was achieved. The method utilizes the selective deposition of silicon oxide by a Liquid Phase Deposition (LPD) method to form a self-aligning implant mask. The mask is then used to implant a buried anti-punchthrough implant channel under and aligned to the gate electrode of the FET. The buried implant reduces the depletion width at the substrate to source/drain junction under the gate electrode but does not increase substantially the junction capacitance under the source/drain contacts, thereby improving punch-through characteristic while maintaining device performance.
Claims6
A field effect transistor having an aligned anti-punchthrough buried implant channel, comprising:
- a semiconductor substrate having a principle surface with device areas and field oxide areas thereon;
- a gate oxide layer on said devices areas composed of thermal oxidation;
- a patterned polysilicon layer forming gate electrodes on said gate oxide layers;
- a buried layer of implanted boron ions in said substrate, below and centered on said gate electrode and forming a buried anti-punchthrough implant channel which is narrower than said gate electrode;
- lightly doped drain (LDD) regions adjacent to said gate electrode;
- sidewall spacers on sidewalls of said gate electrode composed of silicon oxide;
- source/drain regions in said device area, formed by implantation and thereby having a field effect transistor with said buried anti-punchthrough implant channels under and centered on said gate electrode.
Dependencies are inferred from the claim text.