Conductivity enhanced MOS-gated semiconductor devices
AssigneeIntersil Corporation
InventorChristopher Boguslaw Kocon
Life of this patent
Estimating the term…
Abstract
The resistance to current flow through an MOS-gated semiconductor device is reduced by providing a high conductivity region in the path of current through the drain region, but so positioned relative to the p-n voltage blocking junction of the device so as not to adversely affect the voltage blocking capability of the p-n junction. In one embodiment, the drain region is made of higher than normal electrical conductivity, but a diffused, graded p-n junction is provided for extending the low conductivity portion of the drain region bordering the p-n junction further than usual into the drain region.
Claims7
An MOS gated semiconductor device comprising a substrate having a surface, source and drain regions in said substrate at said surface separated by a channel region, said channel and said drain regions adjoining one another at a p-n junction, there being, during operation of said device, a path for current from said source region through said channel region and past first and second successive points in said drain region spaced at respectively greater first and second distances from said p-n junction, said drain region containing dopant atoms of both conductivity types providing a net quantity of fixed charges, the net concentration of said fixed charges being a minimum at said junction and rising continuously with increasing distance from said junction to said first point such that, upon the onset of an avalanching condition caused by the reverse biasing of said p-n junction. a depletion laver spreads into said drain region a maximum distance from said p-n junction past said first point to said second point, where, from said first point towards said second point, a uniform concentration of net fixed charges is present, and said first distance of said first point from said p-n junction is at least 50% of said second distance of said second point from said p-n junction.
An MOS gated semiconductor device comprising a first body of semiconductor material including source and first drain regions separated by a channel region, said channel and drain regions adjoining one another at a p-n junction where the net fixed charge concentration within said drain region increases with distance from said junction into said drain region, and said drain region having a uniform background doping concentration such that, upon the onset of an avalanching condition caused by the reverse biasing of said p-n junction and the spread of a depletion layer into said drain region, the ratio of the uniform background doping concentration of the drain region to the average net fixed charge concentration within said depletion layer is in excess of 1.1.
Dependencies are inferred from the claim text.