Capacitor for a semiconductor memory device

Abstract

A capacitor in a semiconductor substrate with a first insulating layer deposited thereon. The capacitor is formed by etching the first insulating layer to simultaneously form first and second self-aligned contact pads to be electrically connected to the substrate. A second insulating layer is deposited over the first insulating layer. Next, a storage node landing pad is formed in the second insulating layer between bit lines to be electrically connected to the first self-align contact pad. Following the formation of the landing pad, a third insulating layer is formed over the second insulating layer with a thickness large enough to provide a desired capacitance. Then, the third insulating layer is etched until the upper surface of the landing pad is exposed so as to form a storage node contact hole. A first conductive layer is deposited on the surfaces of the storage node contact hole and etched to form capacitor lower electrodes. A capacitor dielectric layer is deposited on the third oxide layer, the capacitor lower electrodes and the landing pad. Therefore, the effective area of the capacitor is increased by forming the capacitor electrodes on the sidewalls of contact holes within the oxide layer on the storage node landing pad.

Dependencies are inferred from the claim text.