Scanning circuit for solid-state imaging device
AssigneeSharp Kabushiki Kaisha
InventorTakashi Watanabe
Life of this patent
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Abstract
A scanning circuit for a solid-state imaging device of the present invention includes a shift register divided into a first stage to an N-th stage, each of the first stage to the N-th stage receiving a first pulse signal which is cyclic and has a plurality of pulses and a second pulse signal which is cyclic and has a plurality of pulses, the first stage receiving an input signal, and an invalid transfer pulse or an effective transfer pulse being output from the first stage to the N-th stage, wherein whether or not the transfer pulse is effective or invalid is determined based on the first pulse signal and the input signal, and the N is an integer of 2 or more.
Claims9
A scanning circuit for a solid-state imaging device, comprising:
- a first shift register divided into a first stage to an N-th stage, each of the first stage to the N-th stage having an input terminal and an output terminal, and the input terminal of the first stage receiving an input signal a first period before a predetermined time;
- a switch group divided into a first stage to an N-th stage, each of the first stage to the N-th stage of the switch group having an input terminal and an output terminal, each of the input terminals of the first stage to the N-th stage of the switch group being connected to each of the output terminals of the first stage to the N-th stage of the first shift register, and each of the first stage to the N-th stage of the switch group being conducted between the input terminal and the output terminal of the switch group based on a pulse signal which becomes active at the predetermined time;
- and
- a second shift register divided into a first stage to an N-th stage, each of the first stage to the N-th stage having an input terminal and an output terminal, and each of the input terminals of the first stage to the N-th stage of the second shift register being connected to each of the output terminals of the first stage to the N-th stage of the switch group,
- wherein the output terminal of the first stage of the second shift register outputs a transfer pulse after an elapse of a second period from the predetermined time, and the N is an integer of 2 or more.
A scanning circuit for a solid-state imaging device, comprising a shift register divided into a first stage to an N-th stage, each of the first stage to the N-th stage receiving a first pulse signal which is cyclic and has a plurality of pulses and a second pulse signal which is cyclic and has a plurality of pulses, the first stage receiving an input signal, and an invalid transfer pulse or an effective transfer pulse being output from the first stage to the N-th stage,
- wherein whether or not the transfer pulse is effective or invalid is determined based on the first pulse signal and the input signal, and the N is an integer of 2 or more.
A scanning circuit for a solid-state imaging device, comprising:
- a first shift register divided into a first stage to an N-th stage, each of the first stage to the N-th stage having an input terminal and an output terminal, each of the first stage to the N-th stage receiving a first pulse signal which is cyclic except for a vicinity of a predetermined time t0 and has a plurality of pulses and a second pulse signal which is cyclic except for the vicinity of the predetermined time t0 and has a plurality of pulses, and the input terminal of the first stage receiving an input signal a period KT before the predetermined time t0;
- a switch group divided into a first stage to an N-th stage, each of the first stage to the N-th stage having an input terminal and an output terminal, the input terminals of the first stage to the N-th stage of the switch group being connected to the output terminals of the first stage to the N-the stage of the first shift register, and each of the first stage to the N-th stage of the switch group being conducted between the input terminal and the output terminal of the switch group based on a pulse signal which becomes active at the predetermined time t0;
- and
- a second shift register divided into a first stage to an N-th stage, each of the first stage to the N-th stage having an input terminal and an output terminal, each of the first stage to the N-th stage receiving the first pulse signal and the second pulse signal, and the input terminals of the first stage to the N-th stage of the second shift register being connected to the output terminals of the first stage to the N-th stage of the switch group,
- wherein the output terminal from an (M·K−(M−1))-th stage to an (M·K−1)-th stage of the second shift register outputs an invalid transfer pulse after an elapse of a period D from the predetermined time t0, and thereafter, the output terminal of an M·K-th stage of the second shift register outputs an effective transfer pulse,
- the T is a positive number,
- the M and K are natural numbers,
- the D is a positive number
- the N is a natural number of 2 or more, and
- the M and K satisfy 1≦M·K≦N.
Dependencies are inferred from the claim text.