# US 6,284,635 B1 · Method for forming titanium polycide gate

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- Number: US 6,284,635 B1
- Document ID: US6284635B1
- Status: Granted
- Kind: B1
- Application number: 09/471,596
- Filed: 1999-12-23
- Granted: 2001-09-04
- Earliest claimed: 1998-12-28
- Assignees: Hyundai Electronics Industries Co., Ltd.
- Inventors: Se Aug Jang
- Web page: https://patentgrep.com/patent/US6284635B1

## CPC

- H10D 64/01312: {the additional layer comprising a metal or metal silicide formed by deposition, i.e. without a silicidation reaction, e.g. sputter deposition}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method for forming a titanium polycide gate, comprising the steps of: forming a gate oxide and a doped polysilicon layer over the semiconductor substrate, in turn; implanting impurity ions into the doped polysilicon layer to form an amorphous phase silicon layer in the surface of the polysilicon layer; forming an amorphous phase titanium silicide layer over the amorphous phase silicon layer; carrying out heat-treatment to transform the amorphous phase titanium silicide layer into a crystalline phase titanium silicide layer and to transform the amorphous phase silicon layer into the crystalline silicon layer; and patterning the crystalline phase titanium silicide layer, the polysilicon layer including the crystalline phase silicon layer and the gate oxide to form the titanium polycide gate.

## Claims

### Claim 1

A method for forming a titanium polycide gate, comprising the steps of:
forming a gate oxide and a doped polysilicon layer over the semiconductor substrate, in turn;
implanting impurity ions into the doped polysilicon layer to form an amorphous phase silicon layer in a surface of the doped polysilicon layer;
forming an amorphous phase titanium silicide layer over the amorphous phase silicon layer;
carrying out heat-treatment to transform the amorphous phase titanium silicide layer into a crystalline phase titanium silicide layer and to transform the amorphous phase silicon layer into a crystalline phase silicon layer; and
patterning the crystalline phase titanium silicide layer, the doped polysilicon layer including the crystalline phase silicon layer and the gate oxide to form the titanium polycide gate.

### Claim 2

The method as claimed in claim, wherein the impurity ions are comprised of any one of Sb, Ge or As.

### Claim 3 (depends on 2)

The method as claimed in claim 2, wherein the impurity ions are implanted at a dose of 1014-1015 ions/cm2 with energy of 40-70 keV.

### Claim 4 (depends on 1)

The method as claimed in claim 1, wherein the heat-treatment is carried out with a rapid thermal process.

### Claim 5 (depends on 4)

The method as claimed in claim 4, wherein the heat-treatment is carried out at a temperature of 700-1,000° C. during 10-30 seconds.