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US 6,284,633 B1Granted
Method for forming a tensile plasma enhanced nitride capping layer over a gate electrode
AssigneeMotorola, Inc.
InventorsRajan Nagabushnam, Stanley M. Filipiak, Bruce Boeck
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Abstract
A tPEN layer (108) having a tensile stress is formed over a conductive gate stack (104-106) provided on a semiconductor substrate. Following the formation of the conductive gate stack (104-106), an anneal is performed. The conductive gate stack includes a metal layer to prevent outgassing and poly depletion during the anneal. Next, a photoresist layer (110) is formed and patterned to form a gate (122, 124).
Claims21
A method of forming a semiconductor device, comprising the sequential steps of:
- forming a gate dielectric layer over a semiconductor substrate;
- forming a doped polysilicon layer over the gate dielectric layer;
- forming a metal-containing layer over the doped polysilicon layer;
- forming a plasma enhanced chemically vapor deposited nitride-containing capping layer at a temperature less than approximately 500° C. over the metal-containing layer, wherein the nitride containing capping layer has a deposited tensile stress greater than approximately 300 MPa, and wherein a combination of the gate dielectric layer, the doped polysilicon layer, the metal-containing layer, and the nitride-containing capping layer form a gate stack;
- annealing the gate stack;
- patterning a resist layer over the gate stack to define a gate pattern;
- and
- etching the gate stack to form a gate.
5 more elements
A method of forming a semiconductor device, comprising the sequential steps of:
- forming a gate dielectric layer over a semiconductor substrate;
- forming a doped polysilicon layer over the gate dielectric layer;
- forming a tungsten silicide layer over the polysilicon layer;
- forming a plasma enhanced chemically vapor deposited silicon nitride antireflective layer on the tungsten silicide layer at a temperature less than approximately 500° C., wherein the silicon nitride antireflective layer has a deposited tinsel stress greater than 300 megapascals;
- annealing the semiconductor substrate to change a phase of the tungsten silicide layer from an amorphous phase to a tetragonal crystalline phase, wherein the silicon nitride antireflective layer prevents outgassing of dopants from the polysilicon layer during annealing;
- patterning a resist layer on the silicon nitride antireflective layer to define exposed and unexposed regions;
- etching exposed regions defined by the photoresist layer to form a gate electrode from remaining portions of the tungsten silicide layer, the doped polysilicon layer, and the gate dielectric layer and an etch stop capping layer from remaining portions of the silicon nitride antireflective layer.
4 more elements
Dependencies are inferred from the claim text.