Angled nitrogen ion implantation for minimizing mechanical stress on side walls of an isolation trench

A method for fabricating a filled isolation trench as part of an integrated circuit on a semiconductor wafer, the method including the steps of:

• A. etching an isolation trench within a layer of epitaxial silicon deposited on top of said semiconductor wafer, said isolation trench having at least one side wall comprised of said epitaxial silicon, and said isolation trench having a bottom wall, wherein said step A further includes the steps of:
• depositing a nitride layer onto said layer of epitaxial silicon;
• and
• etching said isolation trench in said layer of epitaxial silicon through said nitride layer;
• B. implanting nitrogen ions into said at least one side wall of said isolation trench using an angled nitrogen ion implantation process and etching said nitride layer away from said layer of semiconductor material;
• C. thermally growing simultaneously a linear oxide layer of silicon dioxide from said at least one side wall and said bottom wall of said isolation trench and a pad oxide layer onto said layer of semiconductor material;
• D. filling said isolation trench with silicon dioxide using a deposition process to form said filled isolation trench;
• E. densifying said silicon dioxide within said isolation trench with a thermal densification process,
• wherein said step B of implanting said nitrogen ions into said at least one side wall of said isolation trench is performed before said step C of thermally growing said liner oxide layer from said at least one side wall and said bottom wall of said isolation trench such that a radius of a bird's beak formed on said at least one side wall of said isolation trench is minimized,
• wherein said nitrogen ions implanted into said at least one side wall of said isolation trench reduces said radius of said bird's beak formed on said at least one side wall of said isolation trench, and
• wherein said nitrogen ions implanted into said at least one side wall of said isolation trench reduces mechanical stress on said at least one side wall of said isolation trench from said silicon dioxide filling said isolation trench;
• F. polishing down the silicon dioxide, deposited on top of the semiconductor wafer during said step D, to said pad oxide layer using a chemical mechanical polishing (CMP) process;
• G. implanting ions for forming active device regions in said layer of epitaxial silicon having exposed regions of said pad oxide layer;
• H. etching off said pad oxide layer from said layer of epitaxial silicon;
• and
• I. growing gate oxides on said layer of epitaxial silicon when said active device regions formed on said layer of epitaxial silicon is for MOSFETs (Metal Oxide Semiconductor Field Effect Transistors).