Method for fabricating an SOI wafer for low-impedance high-voltage semiconductor components

A method for fabricating an SOI wafer for low-impedance high-voltage semiconductor components, which comprises the following steps:

• (a) producing a first semiconductor wafer from a semiconductor substrate having an outer surface, providing at least one epitaxial layer having first and second mutually opposite outer surfaces, and placing the second outer surface of the at least one epitaxial layer on the outer surface of the semiconductor substrate;
• (b) introducing first trenches into the at least one epitaxial layer and introducing a marking groove through the at least one epitaxial layer to reach the semiconductor substrate;
• (c) depositing a first layer, doped with a dopant of a first conduction type, on the first outer surface of the at least one epitaxial layer, the first trenches and the marking groove;
• (d) providing a second semiconductor wafer having an outer surface, and placing an insulating layer on the outer surface of the second semiconductor wafer;
• (e) direct-bonding the first outer surface of the at least one epitaxial layer, provided with the first doped layer, to the outer surface of the second semiconductor wafer having the insulating layer;
• (f) removing the semiconductor substrate from the second outer surface of the at least one epitaxial layer until reaching a bottom of the marking groove;
• (g) introducing second trenches from the second outer surface of the at least one epitaxial layer until reaching a bottom of the first trenches, and applying a second layer, doped with the dopant of the first conduction type, on walls of the second trenches to produce continuous trenches having walls provided with layers doped with the dopant of the first conduction type;
• and
• (h) filling the continuous trenches with insulating material.