Integration scheme for multilevel metallization structures
AssigneeInternational Business Machines Corporation
InventorsScott A. Seymour, Kenneth J. Stein
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Abstract
A process for forming multilevel metallization structures that improve semiconductor reliability. Multilevel metallization structures are formed through a two-step etch process which alleviates the problem of conductive etch residue forming between metal layers in multilevel structures. The resulting metallization structure has sidewall insulators on selected layers that prevent conductive etch residue from forming between the metal layers. The integration scheme of the present invention is especially applicable to metal-insulator-metal (MIM) capacitors.
Claims20
A process for forming on a substrate a patterned structure having a first conductive layer, a second conductive layer, and an insulator layer between the first and second conductive layers, the process comprising:
- forming in a first etching step the first conductive layer having a first perimeter;
- and
- forming in a single, separate, second etching step the insulator layer and the second conductive layer, the insulator layer and the second conductive layer extending beyond the first perimeter of the first conductive layer.
A metal-insulator-metal stacked capacitor structure comprising:
- a substrate;
- a first conductive layer being disposed on the substrate and having a first perimeter;
- a second conductive layer;
- and
- an insulator layer being disposed between and separating the first and second conductive layers, the insulator layer and the second conductive layer being substantially co-extensive and both extending beyond the first perimeter of the first conductive layer.
Dependencies are inferred from the claim text.