US 6,284,613 B1Granted

Method for forming a T-gate for better salicidation

AssigneeChartered Semiconductor Manufacturing Ltd.

InventorsChivukula Subrahmanyam, Yelehanka Ramachandramurthy Pradeep, Ramakrishnan Rajagopal

Life of this patent

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Abstract

A method for a T-gate and salicide process that allows narrow bottom gate widths below 0.25 μm and wide top gate widths to allow silicide gate contacts on the top of the T-gate. A dummy gate composed of an insulating material is formed over the substrate. Then we form LDD regions adjacent to the dummy gate preferably by ion implanting f (I/I) impurity ions into the substrate using the dummy gate as a mask. A pad oxide layer and dielectric layer are formed over the substrate surface. The dielectric layer over the dummy gate is removed preferably by a CMP process. We then remove the dummy gate to form a gate opening exposing the substrate surface. A gate dielectric layer is formed over the substrate surface in the gate opening. We form a polysilicon layer over the dielectric layer and the substrate surface in the gate opening. The polysilicon layer is patterned to form a T-gate. The dielectric layer is removed. We forming source/drain (S/D) regions adjacent to the T-gate by an Ion implant process. A silicide layer is formed over the T-gate and the substrate to form silicide contacts to the SID regions and gate contacts to the T-gate. Then we form a dielectric layer (ILD) over the T-gate and substrate. We form contact opening through the dielectric layer to expose the S/D regions and T-gate. We form contacts to the S/D regions and to the T-gate.

Claims10

Dependent claims

A method of forming a T-gate used with a salicide process for a semiconductor devices, comprising the steps of:

a) patterning an insulating layer to form a dummy gate over a substrate;
said substrate having a substrate surface;
said insulation layer is patterned by forming a dummy gate resist pattern over said insulating layer using a first gate optical mask;
said dummy gate resist pattern is exposed using said first optical mask, and etching said insulating layer using said dummy gate resist pattern as an etch mask;
b) forming LDD regions adjacent to said dummy gate by ion implanting (I/I) impurity ions into said substrate using said dummy gate as a mask;
c) forming a pad oxide layer over said substrate surface;
d) forming a dielectric layer over said pad oxide layer and said dummy gate and removing said dielectric layer from over said dummy gate;
e) removing said dummy gate forming a gate opening exposing said substrate surface;
f) forming a gate dielectric layer over said substrate surface in said gate opening;
g) forming a gate layer over said dielectric layer and said substrate surface in said gate opening;
h) patterning said gate layer to form a T-gate;
said T-gate filling said gate opening and extending laterally over a portion of said dielectric layer;
said gate layer is patterned by using a T-gate resist pattern formed by using said first gate optical mask by over exposing a resist layer through said first optical gate mask so that the T-gate resist pattern is between 60% and 100% wider than said dummy gate resist;
and
i) removing said dielectric layer and said pad oxide layer leaving said T-gate over said substrate.

12 more elements

A method of forming a T-gate and using a salicide process;

comprising the steps of:
a) forming an insulating layer over a substrate;
b) forming a dummy gate resist pattern over said insulating layer using a first gate optical mask;
c) patterning said insulating layer to form a dummy gate over said substrate;
said substrate having a substrate surface;
d) removing said gate resist pattern;
e) forming LDD regions adjacent to said dummy gate by ion implanting (I/I) impurity ions into said substrate using said dummy gate as a mask;
f) forming a pad oxide layer over said substrate surface;
g) forming a dielectric layer over said pad oxide layer and said dummy gate and removing said dielectric layer from over said dummy gate;
h) removing said dummy gate forming a gate opening exposing said substrate surface;
i) forming a gate dielectric layer over said substrate surface in said gate opening;
said gate opening having a width of between about 0.1 and 0.35 μm.
j) forming a gate layer over said dielectric layer and said substrate surface in said gate opening;
said gate layer is comprised of polysilicon;
k) patterning said gate layer to form a T-gate by forming a T-gate resist pattern and etching said gate layer;
said T-gate filling said gate opening and extending laterally over a portion of said dielectric layer;
said gate layer is pattern using a T-gate resist pattern that is formed by exposing a resist layer using said first gate optical mask;
said T-gate resist pattern is between 60% and 100% wider than said dummy gate resist pattern and where said T-gate resist pattern is formed by overexposing a resist layer thorough said first gate optical mask;
said T-gate has a gate top with a top width of between about 0.35 and 0.5 μm and a top height between 500 and 2000 Å;
and a bottom width between 0.1 and 0.35 μm;
and a bottom height between 1500 and 3500 Å;
l) removing said dielectric layer and said pad oxide layer leaving said T-gate over said substrate;
m) forming source/drain (S/D) regions adjacent to said T-gate by an Ion implant process;
n) forming a silicide layer over said T-gate and said substrate;
to form silicide contacts to said source/drain (S/D) regions and gate contacts to the T-gate;
o) forming a dielectric layer over the T-gate and substrate;
p) forming contact opening through said dielectric layer to expose said source/drain regions and T-gate;
and
q) forming contacts to said source/drain regions and to said T-gate.

26 more elements

Dependencies are inferred from the claim text.

Facts

Application: 09/434,920Filed 5 Nov 1999
Granted: 4 Sep 2001
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

H10D 30/0227
Having source and drain regions or source and drain extensions self-aligned to sides of the gate: having both lightly-doped source and drain…
H10D 30/601
Insulated-gate field-effect transistors [IGFET]: having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs
H10D 30/605
Having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs: having significant overlap between the lightly-doped extensions…
H10D 64/518
Characterised by the conducting layers: characterised by their lengths or sectional shapes