Method to reduce compressive stress in the silicon substrate during silicidation

A method of siliciding source/drain junctions in the manufacture of an integrated circuit comprising:

• providing a polysilicon gate electrode on a semiconductor substrate and associated source/drain extensions within said semiconductor substrate wherein a first nitride layer overlies a top surface of said polysilicon gate electrode;
• depositing a buffer oxide layer overlying said semiconductor substrate and said gate electrode;
• depositing a polysilicon layer overlying said buffer oxide layer;
• depositing a second nitride layer overlying said polysilicon layer;
• polishing back said nitride layer until said buffer oxide layer overlying said gate electrode is exposed whereby a vertical portion of said polysilicon layer is exposed adjacent to said buffer oxide layer forming a vertical sidewall on said gate electrode;
• etching away said exposed polysilicon layer thereby exposing a portion of said buffer oxide layer overlying said source/drain extension wherein remaining horizontal portions of said polysilicon layer overlying said source/drain extensions form source/drain junctions;
• etching away said exposed buffer oxide layer overlying said semiconductor substrate and overlying said gate electrode thereby exposing a portion of said semiconductor substrate and exposing said first nitride layer of said gate electrode;
• thereafter growing an epitaxial-silicon layer overlying said exposed semiconductor substrate;
• thereafter removing said first and second nitride layers;
• and
• siliciding said gate electrode and said source/drain junctions whereby said buffer oxide layer provides compressive stress relief during said siliciding to complete said siliciding of said source/drain junctions in the fabrication of said integrated circuit device.

A method of siliciding source/drain junctions in the manufacture of an integrated circuit comprising:

• providing a polysilicon gate electrode on a semiconductor substrate and associated source/drain extensions within said semiconductor substrate wherein a first nitride layer overlies a top surface of said polysilicon gate electrode;
• thermally oxidizing said gate electrode and said semiconductor substrate whereby an oxide layer is formed overlying said source/drain extensions and whereby sidewalls of said gate electrode are oxidized resulting in a smaller said gate electrode;
• depositing a buffer oxide layer overlying said oxide layer and said gate electrode;
• depositing a doped polysilicon layer overlying said buffer oxide layer;
• depositing a second nitride layer overlying said polysilicon layer;
• polishing back said nitride layer until said buffer oxide layer overlying said gate electrode is exposed whereby a vertical portion of said polysilicon layer is exposed adjacent to said buffer oxide layer forming a vertical sidewall on said gate electrode;
• etching away said exposed polysilicon layer thereby exposing a portion of said buffer oxide layer overlying said source/drain extensions wherein remaining horizontal portions of said polysilicon layer overlying said source/drain extensions form source/drain junctions;
• etching away said exposed buffer oxide layer overlying said semiconductor substrate and overlying said gate electrode thereby exposing a portion of said semiconductor substrate and exposing said first nitride layer of said gate electrode;
• thereafter growing an epitaxial-silicon layer overlying said exposed semiconductor substrate;
• thereafter removing said first and second nitride layers;
• thereafter depositing a metal layer overlying said substrate;
• annealing said substrate whereby said metal layer overlying said polysilicon layer, said polysilicon gate electrode, and said epi-silicon layer is transformed to a metal silicide layer and wherein said metal layer overlying said buffer oxide layer on sidewalls of said polysilicon gate electrode is unreacted whereby said buffer oxide layer provides compressive stress relief during said annealing;
• and
• removing said unreacted metal layer to complete said siliciding of said source/drain junctions in the fabrication of said integrated circuit device.