Formation of an interpoly capacitor structure using a chemical mechanical polishing procedure

A method of simultaneously forming a polysilicon gate structure, and a polysilicon capacitor top plate structure, on an underlying planar top surface of a semiconductor substrate, resulting from a selectively grown, epitaxial silicon region, in a second opening in a composite insulator layer, located underlying said polysilicon gate structure, and resulting from a polysilicon capacitor bottom plate structure, embedded in a first opening in a silicon oxide component of said composite insulator layer, comprising the steps of:

• forming a first silicon oxide layer, on said semiconductor substrate;
• depositing a first silicon nitride layer;
• depositing a second silicon oxide layer;
• forming said first opening in said second silicon oxide layer;
• forming said polysilicon capacitor bottom plate structure, in said first opening;
• depositing a third silicon oxide layer;
• depositing a second silicon nitride layer;
• forming said second opening in said composite insulator layer comprised of said second silicon nitride layer, said third silicon oxide layer, said second silicon oxide layer, said first silicon nitride layer, and said first silicon oxide layer;
• selectively growing said epitaxial silicon region, in said second opening, with the top surface of said epitaxial silicon region, planar with the top surface of said polysilicon capacitor bottom plate structure;
• forming an active device region in said epitaxial silicon region, via creation of a P well region, a threshold voltage adjust region, and a punch through region, in said epitaxial silicon region;
• performing a thermal oxidation procedure to grow a silicon dioxide gate layer, on the top surface of said active device region, and to convert a portion of said second silicon nitride layer, to a silicon oxynitride layer, resulting in a capacitor dielectric layer, comprised of oxidized silicon nitride, on said third silicon oxide layer, overlying said polysilicon capacitor bottom plate structure;
• depositing a polysilicon layer;
• patterning of said polysilicon layer to simultaneously form said polysilicon gate structure, on said silicon dioxide gate layer, and said polysilicon capacitor top plate structure, on the region of said capacitor dielectric layer overlying said polysilicon capacitor bottom plate structure;
• forming a lightly doped source/drain region in an area of said active device region, not covered by said polysilicon gate structure;
• forming insulator spacers on the sides of said polysilicon gate structure, and on the sides of said polysilicon capacitor top plate structure;
• and
• forming a heavily doped source/drain region in an area of said active device region, not covered by said polysilicon gate structure, or by said insulator spacers.