Method for fabricating a semiconductor device

A method for fabricating a semiconductor device, said method comprising the steps of:

• forming a field oxide layer on a first conduction type semiconductor substrate having a cell area where a memory device will be formed and a peripheral circuit area where a driver circuit device will be formed, said field oxide layer defining active and field regions in the device;
• respectively forming first and second gates having capping layers thereon in the cell and peripheral circuit areas after placing a gate insulating layer on said semiconductor substrate;
• forming a first impurity region which serves as source and drain regions in said cell area, and a second impurity region which serves as a lightly doped drain (LDD) region of said driver circuit device in said peripheral circuit area, by ion-implantation of a second conduction type impurity using said capping layers as a mask;
• forming an etching stop layer on said semiconductor substrate to cover said field oxide layer and sides of the first and second gates and forming a sacrificing layer on said etching stop layer to fill a gap between said first and second gates and planarize a surface;
• forming a contact hole by patterning said sacrificing layer and said etching stop layer in a self-alignment manner to expose said first impurity region;
• forming a plug contacting with said first impurity region within said contact hole and removing the remaining sacrificing layer to expose a top of said plug and said etching stop layer;
• forming a third side wall spacer on an exposed side of the top of said plug while forming first and second side wall spacers such that said etching stop layer is respectively interposed between said first and second side wall spacers and the sides of said second and first gates;
• and
• forming a third impurity region to be superposed on the second impurity region of said peripheral circuit area, using said capping layer and said first side wall spacer as the mask, said third impurity region serving as source and drain regions of said driver circuit device.

A method for fabricating a semiconductor device, said method comprising the steps of:

• forming a field oxide layer on a first conduction type semiconductor substrate having a cell area where a memory device will be formed and a peripheral circuit area where a driver circuit device will be formed, said field oxide layer defining active and field regions in the device;
• respectively forming first and second gates having capping layers thereon in the cell and peripheral circuit areas after placing a gate insulating layer on said semiconductor substrate;
• forming a first impurity region which serves as source and drain regions in said cell area, and a second impurity region which serves as a lightly doped drain (LDD) region of said driver circuit device in said peripheral circuit area, by ion-implantation of a second conduction type impurity using said capping layers as a mask;
• forming an etching stop layer on said semiconductor substrate to cover said field oxide layer and sides of the first and second gates and forming a sacrificing layer on said etching stop layer to fill a gap between said first and second gates and planarize a surface;
• forming a contact hole by patterning said sacrificing layer and said etching stop layer in a self-alignment manner to expose said first impurity region;
• forming a plug contacting with said first impurity region within said contact hole and removing the remaining sacrificing layer to expose a top of said plug and said etching stop layer;
• forming a third side wall spacer on an exposed side of the top of said plug while forming first and second side wall spacers such that said etching stop layer is respectively interposed between said first and second side wall spacers and the sides of said second and first gates;
• and
• forming a buffer layer over an entire surface of a structure described above and forming a third impurity region to be superposed on the second impurity region of said peripheral circuit area, using said capping layer and said first side wall spacer as the mask.