US 6,284,585 B1 · Electronic memory device having bit lines with block selector switches

Abstract

An electronic memory device organized into sections which are in turn divided into blocks formed of cells and their associated decoding and addressing circuits, the cells being connected in a predetermined circuit configuration and each block being included between two opposite contact regions which are interconnected by parallel continuous conduction lines referred to as the bit lines. In the present invention, at least one interruption is provided in each bit line near a contact region by inserting a controlled switch which functions as a block selector. Advantageously, the proposed solution allows each block to be isolated individually by enabling or disabling as appropriate the switches of the cascade connected blocks. Also provided is a method of implementing the memory block, as organized into a matrix-like configuration, individually selectable from a plurality of blocks embedded in a memory device, wherein each memory cell is identified by a continuous bit line enabled by at least one block selector, by a broken bit line or ‘segment’ connected to the continuous one through an address device, and by a word line orthogonal to the direction of the bit lines, and formed on a substrate having a first type of conductivity.

Claims6

Dependent claims

A method of reading an electronic memory device that includes:

a block of cells connected in a predetermined circuit configuration, the block including a selected memory cell having first and second conduction terminals and a control terminal;
first and second contact regions positioned at opposite ends of a selected block, the first contact region including first and second contacts;
parallel continuous conduction lines, referred to as bit lines, that interconnect the first and second contact regions, the conduction lines including first and second bit lines coupled to the first and second contacts, respectively;
a plurality of controlled switches respectively situated in the bit lines to function as a block selector and provide interruptions in the bit lines, a selected one of the controlled switches having a control terminal, a first terminal coupled to the first contact, and a second terminal coupled to the first conduction terminal of the selected memory cell;
and
an address transistor coupling the second bit line to the second conduction terminal of the selected memory cell, the method comprising:
applying a read voltage to the second contact and the control terminals of the controlled switch and the selected memory cell;
turning ON the address transistor to couple the second conduction terminal of the selected memory cell to the second contact;
and
coupling the first contact to ground while performing the applying step.

7 more elements

A method of erasing an erasable, programmable electronic memory device that includes:

a matrix of memory cells arranged in rows and columns of cells, the cells of each respective column being connected to each other by a respective bit line and the cells of each respective row being connected to each other by a respective word line;
a plurality of contact regions dividing the matrix into a plurality of cell blocks, each cell block including plural rows and columns of cells and being defined by first and second contact regions placed on opposite sites of the cell block, each of the first and second contact regions including a contact coupled to a respective bit line of the cell block;
for each of the cell blocks, a plurality of block selector switches each having a control terminal connected to a block selector line of the cell block, a first conduction terminal connected to a respective one of the contacts of the first contact region defining the cell block, and a second conduction terminal connected to a respective one of the bit lines of the cell block;
and
an address transistor connected between a first bit line of a selected one of the cell blocks and a selected memory cell of the selected cell block, the selected memory cell being connected between the address transistor and a second bit line of the selected cell block;
the method comprising:
applying a write voltage, during write phase of the selected cell block, to the control terminals of the block selector switches of the selected cell block, to a control terminal of the address transistor, to the first bit line of the cell block, and to a word line coupled to a control terminal of the selected memory cell;
and
holding the second bit line to a voltage less than the write voltage while applying the write voltage.

6 more elements

Dependencies are inferred from the claim text.

Electronic memory device having bit lines with block selector switches

Life of this patent

Electronic memory device having bit lines with block selector switches

Life of this patent

Abstract

Claims6