Back to results
US 6,284,584 B1Granted
Method of masking for periphery salicidation of active regions
AssigneeSTMicroelectronics S.r.l.
InventorsRobert Louis Hodges, Loi Ngoc Nguyen
Life of this patent
Estimating the term…
Abstract
An integrated circuit memory fabrication process and structure, in which salicidation is performed on the periphery (and optionally on the ground lines) of a memory chip, but not on the transistors of the memory cells.
Claims6
A fabrication method, comprising the steps of:
- (a.) providing a substrate having monocrystalline semiconductor material in active areas, at a first surface thereof, which are laterally separated by isolation regions;
- (b.) forming a patterned gate layer overlying and capacitively coupled to portions of ones of said active areas, in locations which define transistor portions of memory cells and also define transistor portions of peripheral logic;
- (c.) forming self-aligned dielectric spacers along the edges of said thin-film layer;
- and
- (d.) depositing and reacting a metal on at least some ones of said active areas, to form a metal silicide at the surfaces of said active areas;
- wherein a masking step is used in connection with said step (d.), in locations such that said step (d.) ultimately provides said metal silicide in said transistor portions of said peripheral logic, but not in said transistor portions of said memory cells.
3 more elements
A fabrication method, comprising the steps of:
- p1 (a.) providing a substrate having monocrystalline semiconductor material in active areas, at a first surface thereof, which are laterally separated by isolation regions;
- (b.) forming a patterned gate layer overlying and capacitively coupled to portions of ones of said active areas, in locations which define transistor portions of memory cells and also define transistor portions of peripheral logic;
- (c.) forming self-aligned dielectric spacers along the edges of said thin-film layer;
- and
- (d.) depositing and reacting a metal on at least some ones of said active areas, to form a metal silicide at the surfaces of said active areas;
- wherein a masking step is used in connection with said step (d.), in locations such that said step (d.) ultimately provides said metal silicide in said transistor portions of said peripheral logic, but not in said transistor portions of said memory cells.
3 more elements
A fabrication method, comprising the steps of:
- (a) providing a substrate having monocrystalline semiconductor material in active areas, at a first surface thereof, which are laterally separated by isolation regions;
- (b) forming a patterned gate layer overlying and capacitively coupled to portions of ones of said active areas, in locations which define transistor portions of memory cells and also define transistor portions of peripheral logic;
- (c) forming self-aligned dielectric spacers along the edges of said thin-film layer;
- and
- (d) depositing and reacting titanium on at least some ones of said active areas, to form a titanium silicide at the surfaces of said active areas;
- wherein a masking step is used in connection with said step (d), in locations such that said step (d) ultimately provides said titanium silicide in said transistor portions of said peripheral logic, but not in said transistor portions of said memory cells.
3 more elements
A fabrication method, comprising the steps of:
- (a) providing a substrate having monocrystalline semiconductor material in active areas, at a first surface thereof, which are laterally separated by isolation regions;
- (b) forming a patterned gate layer overlying and capacitively coupled to portions of ones of said active areas, in locations which define transistor portions of memory cells and also define transistor portions of peripheral logic;
- (c) forming self-aligned dielectric spacers along the edges of said thin-film layer;
- and
- (d) depositing and reacting titanium on at least some ones of said active areas, to form a titanium silicide at the surfaces of said active areas;
- wherein a masking step is used in connection with said step (d), in locations such that said step (d) ultimately provides said titanium silicide in said transistor portions of said peripheral logic, but not in said transistor portions of said memory cells.
3 more elements
Dependencies are inferred from the claim text.