Method of manufacture of a stacked electrostatic ink jet printer
AssigneeSilverbrook Research Pty Ltd
InventorKia Silverbrook
Life of this patent
Estimating the term…
Abstract
This patent describes a method of manufacturing a stacked electrostatic ink jet print head wherein an array of nozzles are formed on a substrate utilizing planar monolithic deposition, lithographic and etching processes. Multiple ink jet heads are formed simultaneously on a single planar substrate such as a silicon wafer. The print heads can be formed utilizing standard VLSI/ULSI processing and can include integrated drive electronics formed on the same substrate. The drive electronics preferably being of a CMOS type. In the final construction, ink can be ejected from the substrate substantially normal to the substrate plane.
Claims10
A method of manufacture of an ink jet print head arrangement including a series of nozzle chambers, said method comprising the steps of:
- (a) utilising an initial semiconductor wafer having an electrical circuitry layer thereon including etched vias for interconnection of said circuitry with subsequent layers;
- (b) repeatedly depositing a series of planar layers on said electrical circuitry layer, said planar layers including a first conductive layer, a second conductive layer and an intermediate compressible non conductive layer;
- (c) etching said planar layers so as to form a series of stacked alternating structures;
- (d) isolating at least one first edge of said stacked alternating structure;
- (e) etching said second conductive layer and said intermediate compressible layer along said edge so as to expose said first conductive layer;
- (f) isolating a second edge of said stacked alternating structure;
- (g) etching said first conductive layer and said intermediate compressible layer along said second edge so as to expose said second conductive layer;
- (h) depositing and etching a third conductive layer having first portions interconnected along said first edge with said first conductive layer and a second portion interconnected along said second edge with said second conductive layer, said first and second portions being interconnected with corresponding portions in said electrical circuitry layer;
- (i) depositing and etching a sacrificial material layer on said wafer, said etching forming a mould for a subsequent nozzle chamber layer;
- (j) depositing and etching an insert material layer over said sacrificial layer so as to form a nozzle chamber surrounding said conductive layers in addition to an ink ejection hole;
- (k) etching an ink supply channel through portions of said wafer to interconnect with said nozzle chamber;
- and
- (l) etching away said sacrificial material layer.
Dependencies are inferred from the claim text.