Integrated processor and programmable data path chip for reconfigurable computing

A reconfigurable computing method using an adaptive compute engine including a microprocessor, a memory, and an array of reconfigurable logic elements having fine-grain reconfigurable control logic and coarse-grain reconfigurable datapath logic, the method comprising the steps of:

• executing instructions on the microprocessor;
• in response to one or more instructions, loading multiple sets of configuration data into the memory;
• passing data to the coarse-grain reconfigurable datapath logic;
• and
• passing control information to the fine-grain reconfigurable datapath logic.

An integrated circuit, comprising:

• fine-grain reconfigurable control logic;
• coarse-grain reconfigurable datapath logic;
• and
• memory means coupled to the reconfigurable control logic and the reconfigurable datapath logic for defining multiple configurations of the reconfigurable control logic and the reconfigurable datapath logic;
• wherein said memory means comprises means for simultaneously addressing multiple memory locations located in different memory rows and different memory columns to write identical data into the multiple memory locations, whereby an amount of data needed to completely configure at least one of said reconfigurable control logic and said reconfigurable datapath logic is substantially reduced.

A reconfigurable computing method using an adaptive compute engine including a microprocessor, a memory, and an array of reconfigurable logic elements, the method comprising the steps of:

• executing instructions on the microprocessor;
• loading multiple sets of configuration data into memory in response to one or more instructions;
• and
• simultaneously addressing multiple memory locations located in different memory rows and different memory columns to write identical data into the multiple memory locations, whereby an amount of data needed to completely configure the logic elements is substantially reduced.