Method and apparatus for floating point operations and format conversion operations

An apparatus for converting numbers between an integer format and a floating point format including an exponent portion and a fraction portion, the apparatus comprising:

• a shifter to receive a floating point number in said floating point format, wherein the shifter includes additional register positions to the right of the rightmost position required by a floating point arithmetic operation to accommodate a right shift beyond a data path width required by a floating point arithmetic operation;
• a first selection circuit to align a number with respect to the additional register positions according to whether a current operation is an arithmetic operation or a conversion operation;
• a second selection circuit to select either an exponent of a floating point number to be added to another floating point number or two exponent constant values based upon whether the current operation is an arithmetic operation or a conversion operation;
• a subtractor to receive the two exponent constant values and to produce two difference values by subtracting an exponent of the floating point number to be converted from each of the two exponent constant values;
• a third selection circuit to select one of the two difference values as an indication of a number of bit positions to shift right based upon whether the exponent of the floating point number to be converted is greater than or equal to a certain number;
• and
• a shift control unit to control the shifter to shift fraction portion data of the floating point number into the additional register positions based on which of the two difference values is selected.

A processor comprising:

• a floating point circuit to perform arithmetic of floating point numbers and conversion of numbers between a floating point format, including an exponent portion and a fraction portion, and an integer format, wherein a data path width required for a conversion operation is greater than a data path width required for an arithmetic operation, the floating point circuit comprising:
• a right shift circuit to receive a floating point number to be converted, wherein the right shift circuit includes additional bit positions to the right of a rightmost bit of the floating point number to be converted, and wherein when an operation to be performed is a conversion operation, the right shift circuit latches the floating point number to be converted so that the additional bit positions are unoccupied;
• a left shift circuit to receive an integer number to be converted, wherein the left shift circuit includes additional bit positions to the right of a rightmost bit of the integer number to be converted, and wherein when the operation to be performed is a conversion operation, the left shift circuit latches the integer number so that the additional bit positions are occupied;
• and
• a right shift control circuit to control the right shift circuit to output an integer number with a least significant bit position having a first alignment in response to the exponent portion of the floating point number having a first magnitude, and to output an integer number with a least significant bit position having an alignment different from the first alignment, in response to said exponent portion having a second magnitude.

A processor comprising a floating point unit to perform arithmetic of floating point numbers and conversion of numbers between a floating point format, including an exponent portion and a fraction portion, and an integer format, the floating point unit including:

• a right shifter to receive a floating point number to be converted, wherein the right shifter includes additional bit positions to the right of a rightmost bit of the floating point number to be converted, and wherein when an operation to be performed is a conversion operation, the right shifter latches the floating point number to be converted so that the additional bit positions are unoccupied;
• a left shifter to receive an integer number to be converted, wherein the left shifter includes additional bit positions to the right of a rightmost bit of the integer number to be converted, and wherein when the operation to be performed is a conversion operation, the left shifter latches the integer number so that the additional bit positions are occupied;
• a first selection circuit to select either an exponent of a floating point number to be added to another floating point number or two exponent constant values based upon whether the floating point circuit is performing an arithmetic operation or a conversion operation;
• a subtractor to receive the two exponent constant values and to output two difference values, wherein the subtractor separately subtracts an exponent of the floating point number to be converted from each of the two exponent constant values;
• a second selection circuit to select one of the two difference values as an indication of a number of bit positions to shift right based upon whether the exponent of the floating point number to be converted is greater than or equal to a certain number;
• and
• a right shift control circuit to control the right shifter to output fraction portion bits into the additional bit positions based on which of the two difference values is selected.

A method for using a floating point arithmetic circuit to perform a conversion between a floating point format and an integer format, comprising:

• receiving a floating point number in the floating point arithmetic circuit,
• determining whether a shift operation required to align the floating point number for integer representation will cause significant bits to be shifted beyond a bit position represented by an extreme rightmost bit of the floating point number,
• if it is determined that the shift operation required to align the floating point number for integer representation will cause any bits to be shifted beyond the bit position, using a second conversion constant to determine a number of bit positions to shift,
• else, using a first conversion constant to determine the number of bit positions to shift, wherein the second conversion constant is larger than the first conversion constant.