Semiconductor memory device having a delay circuit for generating a read timing
AssigneeNEC Corporation
InventorsAtsushi Nakagawa, Hiroyuki Takahashi
Life of this patent
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Abstract
A delay circuit in a semiconductor memory device generates a sense amplifier enable signal having a delay time with respect to the timing of selection of one of memory cells. The delay time corresponds to the largest read time for the memory cell located at the most distant position and has an irregularity reflecting an irregularity in threshold voltage of nMOSFET transfer gates in each memory cell, which affects the read time. An optimum timing for the sense amplifier enable signal can be obtained by the delay circuit irrespective of the irregularity in the threshold voltage of the nMOSFET transfer gates.
Claims16
A semiconductor memory device comprising a memory cell array including a plurality of memory cells, an address decoder for decoding an address signal to select one of said memory cells, a read circuit for responding to a sense amplifier enable signal to latch read data from said one of said memory cells at a first timing, a delay circuit for responding to selection of said one of said memory cells to generate a delay signal for specifying said first timing, said delay signal having a delay time reflecting an irregularity in a characteristic of either of a pMOSFET and an nMOSFET in said memory cell.
A semiconductor device comprising a first circuit for responding to a first activating signal to output a first data signal to a data line, a second circuit for responding to a second activating signal to latch said first data signal from said data line, a delay circuit for responding to said first activating signal to generate said second activating signal having a delay time with respect to said first activating signal, said delay time reflecting an irregularity in a characteristic of either of a pMOSFET and an nMOSFET in said first circuit.
A delay circuit comprising a plurality of cascaded inverters each including a first MOSFET and a second MOSFET, a third MOSFET disposed for each of said inverters, having a first conductivity type and connected in series with a corresponding one of said inverters between a first source line and a second source line, a fourth MOSFET having a first conductivity type and forming a current mirror in combination with said third MOSFET, and a fifth MOSFET having a second conductivity type and connected in series with said fourth MOSFET between said first source line and said second source line to carry a fixed current for said fifth MOSFET.
A delay circuit comprising a plurality of cascaded inverters connected in parallel with one another and each including a first MOSFET and a second MOSFET, a third MOSFET having a first conductivity type and connected in series with said cascaded, parallel inverters between a first source line and a second source line, a fourth MOSFET having a first conductivity type and forming a current mirror in combination with said third MOSFET, and a fifth MOSFET having a second conductivity type and connected in series with said fourth MOSFET between said first source line and said second source line to carry a fixed current for said fifth MOSFET.
Dependencies are inferred from the claim text.