Chips arranged in plurality of planes and electrically connected to one another
AssigneePac Tech—Packaging Technologies GmbH
InventorsHans-Hermann Oppermann, Elke Zakel, Ghassem Azdasht, Paul Kasulke
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Abstract
Process for the formation of a spatial chip arrangement having several chips (32, 36, 37, 38, 39) arranged in several planes and electrically connected to one another, in which the chips are connected via their peripheral connection surfaces (33) to assigned conducting paths (23) of a conducting-path structure (24, 25) arranged on at least one carrier substrate (21, 22) by the chips being arranged either transverse to the longitudinal extent of the carrier substrate or parallel to the longitudinal extent of the flexibly constructed carrier substrate, as well as a spatial chip arrangement that is formed by means of this process.
Claims7
A spacial chip arrangement comprising
- a plurality of chips arranged in a plurality of planes and electrically connected to one another,
- the plurality of chips include each a peripheral connection surface;
- a conducting structure includes a conducting path structure being an integral part of a carrier substrate and having conductive paths;
- the peripheral connection surfaces are directly electrically connected to assigned conducting paths by melted solder bumps;
- the connection surfaces are arranged in a plane transverse to the carrier substrate;
- the conducting path structure is arranged on at least one side of the carrier substrate and extends parallel to a surface plane thereto and the chips being arranged transverse to the carrier substrate;
- wherein the carrier substrate is formed of a flexible material comprises a plurality of carrier substrates, and wherein the plurality of chips are connected via several rows of peripheral connection surfaces to the plurality of carrier substrates which are assigned respectively to a row of connection surfaces.
Dependencies are inferred from the claim text.