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US 6,281,552 B1Granted
Thin film transistors having ldd regions
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorsRitsuko Kawasaki, Hidehito Kitakado, Kenji Kasahara, Shunpei Yamazaki
Life of this patent
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Abstract
To improve the operation characteristic and reliability of a semiconductor device by optimizing the structure of bottom gate type or inverted stagger type TFTs arranged in circuits of the semiconductor device in accordance with the function of the respective circuits. At least LDD regions that overlap with a gate electrode are formed in an N channel type TFT of a driving circuit, and LDD regions that do not overlap with the gate electrode are formed in an N channel type TFT of a pixel matrix circuit. The concentration of the two kinds of LDD regions is differently set from each other, to thereby obtain the optimal circuit operation.
Claims20
A semiconductor device comprising:
- a pixel portion and a driver circuit for the pixel portion on a same substrate;
- a first n-channel thin film transistor being formed in the pixel portion and including:
- a first active layer;
- at least a first LDD region in the first active layer;
- a first gate insulating film being formed between the first active layer and the substrate;
- a first gate electrode being formed between the first gate insulating film and the substrate;
- a second n-channel thin film transistor being formed in the driver circuit and including:
- a second active layer;
- at least a second LDD region in the second active layer;
- a second gate insulating film being formed between the second active layer and the substrate;
- a second gate electrode being formed between the second gate insulating film and the substrate,
- wherein the first LDD region of the first n-channel thin film transistor in the pixel portion is not overlapped with the first gate electrode,
- wherein the second LDD region of the second n-channel thin film transistor in the driver circuit is overlapped with the second gate electrode,
- wherein the first LDD region includes an n-type impurity at a first concentration while the second LDD region includes the n-type impurity at a second concentration,
- wherein the second concentration is higher than the first concentration.
12 more elements
A method of manufacturing a semiconductor device including a pixel portion and a driver circuit for the pixel portion on a same substrate, said method comprising the steps of:
- forming a first n-channel thin film transistor in the pixel portion and a second n-channel thin film transistor in the driver circuit,
- said first n-channel thin film transistor including:
- a first active layer;
- at least a first LDD region in the first active layer;
- a first gate insulating film being formed between the first active layer and the substrate;
- a first gate electrode being formed between the first gate insulating film and the substrate;
- said second n-channel thin film transistor including:
- a second active layer;
- at least a second LDD region in the second active layer;
- a second gate insulating film being formed between the second active layer and the substrate;
- a second gate electrode being formed between the second gate insulating film and the substrate,
- wherein the first LDD region of the first n-channel thin film transistor in the pixel portion is not overlapped with the first gate electrode,
- wherein the second LDD region of the second n-channel thin film transistor in the driver circuit is overlapped with the second gate electrode,
- wherein the first LDD region includes an n-type impurity at a first concentration while the second LDD region includes the n-type impurity at a second concentration,
- wherein the second concentration is higher than the first concentration.
12 more elements
A semiconductor device comprising:
- a pixel portion and a driver circuit for the pixel portion on a same substrate;
- a first bottom gate type n-channel thin film transistor being formed in the pixel portion and including:
- a first gate electrode on an insulating surface;
- a first semiconductor island being formed over the first gate electrode having a first gate insulating film interposed therebetween, said first semiconductor island including a first source region, a first drain region, a first channel region, and a pair of first lightly doped drain (LDD) regions;
- at least a CMOS circuit being formed in the driver circuit and including a second bottom gate type n-channel thin film transistor and a bottom gate type p-channel thin film transistor;
- said second bottom gate type n-channel thin film transistor including:
- a second gate electrode on the insulating surface;
- a second semiconductor island being formed over the second gate electrode having a second gate insulating film interposed therebetween, said second semiconductor island including a second source region, a second drain region, a second channel region, and a pair of second LDD regions;
- said bottom gate type p-channel thin film transistor including:
- a third gate electrode being formed on the insulating surface;
- a third semiconductor island being formed over the third gate electrode having a third gate insulating film interposed therebetween, said third semiconductor island including a third source region, a third drain region, and a third channel region,
- wherein each of the first LDD regions of the first bottom gate type n-channel thin film transistor in the pixel portion is not overlapped with the first gate electrode,
- wherein each of the second LDD regions of the second bottom gate type n-channel thin film transistor in the driver circuit is overlapped with the second gate electrode,
- wherein each of the first LDD regions includes an n-type impurity at a first concentration while each of the second LDD regions includes the n-type impurity at a second concentration,
- wherein the second concentration is higher than the first concentration.
12 more elements
Dependencies are inferred from the claim text.