System and method for forming a uniform thin gate oxide layer
AssigneeAgere Systems Guardian Corp.
InventorsDavid C. Brady, Isik C. Kizilyalli, Yi Ma, Pradip K. Roy
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AssigneeAgere Systems Guardian Corp.
InventorsDavid C. Brady, Isik C. Kizilyalli, Yi Ma, Pradip K. Roy
Estimating the term…
This invention includes a novel synthesis of a three-step process of growing, depositing and growing SiO2 under low pressure, e.g., 0.2-10 Torr, to generate high quality, robust and reliable gate oxides for sub 0.5 micron technologies. The first layer, 1.0-3.0 nm is thermally grown for passivation of the Si-semiconductor surface. The second deposited layer, which contains a substantial concentration of a hydrogen isotope, such as deuterium, forms an interface with the first grown layer. During the third step of the synthesis densification of the deposited oxide layers occurs with a simultaneous removal of the interface traps at the interface and growth of a stress-modulated SiO2 occurs at the Si/first grown layer interface in the presence of a stress-accommodating interface layer resulting in a planar and stress-reduced Si/SiO2 interface. The entire synthesis is done under low-pressure (e.g., 0.2-10 Torr) for slowing down the oxidation kinetics to achieve ultrathin sublayers and may be done in a single low-pressure furnace by clustering all three steps.
A semiconductor wafer having a gate dielectric located thereon and having a thickness of less than about 7.5 nm, comprising:
Dependencies are inferred from the claim text.