Process of manufacturing silicon-on-insulator chip having an isolation barrier for reliability

A process of manufacturing a silicon-on-insulator semiconductor chip having a peripheral edge, the process comprising the steps of:

• providing a substrate;
• depositing an oxide layer on the substrate;
• depositing a silicon layer on the oxide layer;
• depositing a passivation layer on the silicon layer;
• forming an isolation barrier, including a groove, (a) slightly inward of the peripheral edge, in a position to surround completely the active area of the chip once created, and (b) through the silicon layer and through the oxide layer and partially into the substrate to prohibit impurities in the oxide layer outside the isolation barrier from diffusing into the oxide layer inside the isolation barrier;
• and
• depositing a barrier material (a) over the passivation layer, and (b) in the groove presenting an additional barrier to impurities in the oxide layer outside the groove from diffusing into the oxide layer inside the groove.

A process of manufacturing a silicon-on-insulator semiconductor chip having a peripheral edge, the process comprising the steps of:

• providing a substrate;
• depositing an oxide layer on the substrate;
• depositing a silicon layer on the oxide layer;
• forming an isolation barrier, including a groove, (a) slightly inward of the peripheral edge, in a position to surround completely the active area of the chip once created, and (b) through the silicon layer and through the oxide layer and partially into the substrate to prohibit impurities in the oxide layer outside the isolation barrier from diffusing into the oxide layer inside the isolation barrier;
• depositing a passivation layer on the silicon layer and in the groove;
• and
• depositing a barrier material on the passivation layer, over the silicon layer and in the groove, presenting an additional barrier to impurities in the oxide layer outside the groove from diffusing into the oxide layer inside the groove.