Disposable spacers for improved array gapfill in high density DRAMs
AssigneesInfineon Technologies AG, International Business Machines Corporation, Infineon Technologies North America Corp.
InventorsHiroyuki Akatsu, Ramachandra Divakaruni, Gill Yong Lee
Life of this patent
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Abstract
There is disclosed the process of forming a gate conductor for a semiconductor device. The process begins with the step of providing a semiconductor substrate having a gate stack formed thereon, the gate stack including a sidewall. Dielectric spacers are formed on the gate conductor sidewalls, the dielectric spacers comprising an inner spacer and an outer spacer, the outer spacer being of a doped glass material. Ions are implanted into the semiconductor substrate outwardly of the dielectric spacers. The outer spacers are then removed.
Claims20
The process of forming gate conductors for improved gapfill in a high density semiconductor memory device comprising the steps of:
- providing a semiconductor substrate having an array region and a support region, each including gates stacks formed thereon, each gate stack including a sidewall;
- forming dielectric spacers on the gate conductor sidewalls, the dielectric spacers comprising an inner spacer and an outer spacer, the outer spacer defining an offset in the support region;
- implanting ions into the semiconductor substrate outwardly of the dielectric spacers;
- and
- removing the outer spacer for improved array gapfill characteristics.
The process of forming gate conductors for improved gapfill in a high density semiconductor memory device comprising the steps of:
- providing a semiconductor substrate having an oxide layer, defining an array region and a support region, and having gate stacks formed thereon each gate stack including a layer of polysilicon on the oxide layer, a conductor material layer on the polysilicon layer and a nitrite cap layer on the conductor material layer, and a nitrite prespacer surrounding at least part of the gate stack to define a gate conductor sidewall;
- forming dielectric spacers on the gate conductor sidewalls, the dielectric spacers comprising an inner spacer and an outer spacer, the outer spacer defining an offset in the support region;
- implanting ions into the semiconductor substrate outwardly of the dielectric spacers;
- and
- removing the outer spacers for improved array gapfill characteristics.
Dependencies are inferred from the claim text.