Self-aligned silicide process for forming silicide layer over word lines in DRAM and transistors in logic circuit region

A self-aligned silicide process for forming a silicide layer over word lines in a memory cell region of a substrate and a silicide layer over transistors in a logic circuit region of the substrate, comprising the steps of:

• forming a first transistor and a second transistor in the substrate, wherein the first transistor is formed inside the logic circuit region and includes a first gate conductive layer and a first source/drain region, and wherein the second transistor is formed inside the memory cell region and includes a second gate conductive layer and a second source/drain region;
• forming a blocking layer over the first transistor, the second transistor and the substrate;
• forming a photoresist layer over the blocking layer;
• patterning the photoresist layer to remove photoresist material from the logic circuit region;
• etching back the photoresist layer in the memory cell region to expose the blocking layer above the second gate conductive layer so that a residual photoresist layer becomes a patterned photoresist layer;
• etching the blocking layer to expose the first gate conductive layer, the first source/drain region and the second gate conductive layer, while using the patterned photoresist layer as an etching mask;
• removing the patterned photoresist layer so that the second source/drain region is still covered by a remaining blocking layer;
• and
• forming a metal silicide layer over the first gate conductive layer, the first source/drain region and the second gate conductive layer.

A self-aligned silicide process for forming a silicide layer over word lines in a memory cell region of a substrate and a silicide layer over transistors in a logic circuit region of the substrate, comprising the steps of:

• forming a first transistor and a second transistor in the substrate, wherein the first transistor is formed inside the logic circuit region and includes a first gate conductive layer and a first source/drain region, and wherein the second transistor is formed inside the memory cell region and includes a second gate conductive layer and a second source/drain region;
• forming a blocking layer over the first transistor, the second transistor and the substrate;
• forming a photoresist layer over the blocking layer;
• providing a photomask, wherein a transparency of the photomask in a region that corresponds to the memory cell region is only about 20% to 80% of a transparency of the photomask in a region that corresponds to the logic circuit region;
• exposing the photoresist layer through the photomask;
• developing the photoresist layer to remove the photoresist layer in the logic circuit region and the photoresist layer over the second gate conductive layer so that a residual photoresist layer remains over the second source/drain region and becomes a patterned photoresist layer;
• etching the blocking layer to expose the first gate conductive layer, the first source/drain region and the second gate conductive layer, while using the patterned photoresist layer as an etching mask;
• removing the patterned photoresist layer, wherein the second source/drain region is still covered by a remaining blocking layer;
• and
• forming a metal silicide layer over the first gate conductive layer, the first source/drain region and the second gate conductive layer.