Wafer flattening process and system
AssigneeYasuhiro Horiike and SpeedFam Co, Ltd.
InventorsMichihiko Yanagisawa, Shinya Iida, Yasuhiro Horiike
Life of this patent
Estimating the term…
Loading patent…
AssigneeYasuhiro Horiike and SpeedFam Co, Ltd.
InventorsMichihiko Yanagisawa, Shinya Iida, Yasuhiro Horiike
Estimating the term…
A wafer flattening process and system enables a reduction of the surface roughness of a wafer resulting from local etching. A silicon wafer W is brought into close proximity to a nozzle portion 20 to feed SF6 gas to an alumina discharge tube 2, a plasma generator 1 is used to cause plasma discharge and spray a first activated species gas from the nozzle portion 20 to the silicon wafer W side, an X-Y drive mechanism 4 is used to make the nozzle portion 20 scan to perform a local etching step. Then the silicon wafer W is moved away from the nozzle portion 20 and O2 gas and CF4 gas are fed to the alumina discharge tube. At this time, the O2 gas is set to be greater in amount than the CF4 gas. When this mixed gas is made to discharge to generate plasma, a second activated species gas diffuses from the nozzle portion 20 to the entire surface of the silicon wafer W. Since there is a larger amount of O radicals than F radicals, the reaction product resulting from the O radicals deposit in fine depressions causing roughness and the front surface of the silicon wafer W is smoothed.
A wafer flattening process comprising:
Dependencies are inferred from the claim text.