US 6,280,640 B1 · Process for manufacturing a chip carrier substrate

Abstract

A process for manufacturing a chip carrier substrate, the process including the steps of providing a first layer of copper conductor on a substrate, forming a first layer of barrier metal on the first layer of copper conductor, forming a layer of aluminum on the first layer of barrier metal, forming a second barrier metal on the aluminum layer, patterning the top barrier metal in the form of studs, anodizing the aluminum unprotected by the top barrier metal, removing the aluminum oxide and patterning the first copper layer, removing all the exposed barrier metal; surrounding the studs and the copper conductor with a polymeric dielectric; polishing the polymeric dielectric to expose the studs; and forming a second layer of copper conductor on the planar polymeric dielectric.

Claims23

Dependent claims

A process for manufacturing a chip carrier substrate, the process comprising the steps of:

a) providing at least first and second layers of copper conductors on a base;
b) electrically connecting said layers of copper conductors by aluminum studs formed by anodization;
c) providing an electrically connecting layer of barrier metal between each aluminum stud and interconnected conductors, before said step of electrically connecting;
and
d) surrounding said studs and at least said first layer of copper conductor with a polymeric dielectric.

2 more elements

A process for manufacturing a chip carrier substrate, the process comprising the steps of:

a) providing a first layer of copper conductor on a substrate;
b) forming a first layer of barrier metal on said first layer of copper conductor;
c) forming a layer of aluminum on the first barrier metal layer;
d) providing a barrier metal mask in the form of studs on the aluminum layer;
e) anodizing the aluminum unprotected by the barrier metal mask;
f) removing the aluminum oxide;
g) etching the first layer of copper conductor;
h) surrounding said studs and said etched copper conductor with a polymeric dielectric;
i) polishing said polymeric dielectric to expose tops of said studs;
j) forming an adhesion/barrier metal layer on said polished polymeric dielectric and exposed stops of studs;
k) forming a second layer of copper on said adhesion/barrier metal layer.

8 more elements

Dependencies are inferred from the claim text.

Process for manufacturing a chip carrier substrate

Life of this patent

Process for manufacturing a chip carrier substrate

Life of this patent

Abstract

Claims23