High bandwidth flash memory that selects programming parameters according to measurements of previous programming operations
AssigneeMulti Level Memory Technology
InventorsSau C. Wong, Hock C. So
Life of this patent
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AssigneeMulti Level Memory Technology
InventorsSau C. Wong, Hock C. So
Estimating the term…
A multi-level non-volatile memory includes one or more arrays of memory cells including storage cells and dummy cells. The memory observes or measures write operations that write dummy values to the dummy cells and from the observations or measurements selects parameters such as programming voltages or the duration of program cycles. The selection of parameters optimizes write precision within the available access time of a high bandwidth memory. Accessing dummy cells also allows the memory to reach a steady state before writing or reading of data begins. In particular, multiple pipelines sequentially start write operations, and writing of data begins when an equilibrium number of pipelines are performing write operations. Similarly, multiple read operation start before the reading of data for actual use. The stabilization is particularly critical when the pipelines share a power source.
A non-volatile memory comprising:
A multi-level, non-volatile memory comprising a plurality of pipelines, wherein each pipeline comprises:
A write process for a multi-level non-volatile memory, comprising:
Dependencies are inferred from the claim text.