Isolated well transistor structure for mitigation of single event upsets

An SEU signal blocking and dissipation subcircuit comprised of:

• (a) a blocking subcircuit using transistors that are entirely of type NMOS which are all contained within a single p-well, said blocking subcircuit having one external source node which is connected to the sources of one or more of the subcircuit's transistors, one external drain node which is connected to one or more drains of the subcircuit's transistors, an external p-well node connected to the common p-well, and a set of external gate nodes connected to the subcircuit's transistor gates and having bias applied to the p-well node such that the blocking subcircuit's p-well is at a potential with respect to the blocking subcircuit's external source node the magnitude of which is less than 40% of the potential from the supply voltage to ground and having bias applied to said blocking subcircuit's external gate nodes such that whenever any circuit connected to the blocking subcircuit's external drain node is in an SEU sensitive state, the current path(s) through the blocking subcircuit from the external drain node to the external source node will be in a high impedance (off) state;
• and
• (b) a shunt subcircuit connected between the blocking subcircuit's external drain node and another circuit node which has a static bias potential with respect to the blocking subcircuit's external source node the magnitude of which is less than 40% of the potential from the supply voltage to ground and said shunt subcircuit having a current capability which is less than 50% of any low impedance circuit path from the blocking subcircuit's external source node to the negative circuit power supply or ground.

An SEU signal blocking and dissipation subcircuit comprised of:

• (a) a blocking subcircuit using transistors that are entirely of type PMOS which are all contained within a single n-well, said blocking subcircuit having one external source node which is connected to the sources of one or more of the subcircuit's transistors, one external drain node which is connected to one or more drains of the subcircuit's transistors, an external n-well node connected to the common n-well, and a set of external gate nodes connected to the subcircuit's transistor gates and having bias applied to the blocking subcircuit's n-well node such that the n-well is at a potential with respect to the blocking subcircuit's external source node the magnitude of which is less than 40% of the potential from the supply voltage to ground and having bias applied to said blocking subcircuit's external gate nodes such that whenever any circuit connected to the blocking subcircuit's external drain node is in an SEU sensitive state, the current path(s) through the blocking subcircuit from the external drain node to the external source node will be in a high impedance (off) state;
• and
• (b) a shunt subcircuit connected between the blocking subcircuit's external drain node and another circuit node which has a static bias potential with respect to the blocking subcircuit's external source node the magnitude of which is less then 40% of the potential from the supply voltage to ground and said shunt subcircuit having a current capability which is less than 50% of any low impedance circuit path from the blocking subcircuit's external source node to the positive circuit power supply or Vdd.

A circuit comprising in combination:

• (a) a plurality of single event upset (SEU) sensitive transistors;
• (b) a circuit node driven by said plurality of single event upset (SEU) sensitive transistors;
• (c) at least one single event (SEU) immune transistor disposed between said single event upset (SEU) sensitive transistors and said circuit node driven by said plurality of single event (SEU) sensitive transistors;
• (d) and with bias being supplied to the single event upset (SEU) immune transistor(s) such that it is in a high impedance state at any time that bias to said plurality of single event upset (SEU) sensitive transistors places any of said plurality of single event upset (SEU) sensitive transistors in a single event upset (SEU) sensitive state.