Flip-chip switching regulator
AssigneeVolterra Semiconductor Corporation
InventorsAndrew J. Burstein, Charles Nickel
Life of this patent
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Abstract
A voltage regulator with an input terminal and an output terminal has a printed circuit board, a substrate mounted on the printed circuit board, and a first flip-chip type integrated circuit chip mounted on the substrate. The first integrated circuit chip includes a first power switch fabricated therein to alternately couple and decouple the input terminal to the output terminal. A filter is disposed to provide a substantially DC voltage at the output terminal, and a control circuit controls the power switch to maintain the DC voltage substantially constant.
Claims43
A voltage regulator having an input terminal and an output terminal, comprising:
- a printed circuit board;
- a substrate mounted on the printed circuit board;
- a first flip-chip type integrated circuit chip mounted on the substrate, the first integrated circuit chip including a first power switch fabricated therein to alternately couple and decouple the input terminal to the output terminal, wherein the flip-chip type integrated circuit chip includes a p-type region and an n-type region, and the first power switch includes a plurality of p+ regions fabricated in the n-type region in a first array, and a plurality of n+ regions fabricated in the p-type region in a second array, and wherein alternating p+ regions are connected to the input terminal and to an intermediate terminal, and alternating n+ regions chip are connected to the intermediate terminal and to ground;
- a filter disposed to provide a substantially DC voltage at the output terminal;
- and
- a control circuit to control the power switch to maintain the DC voltage substantially constant.
An integrated circuit chip with a power switch for a voltage regulator fabricated thereon, comprising:
- a substrate having a first plurality of doped regions and a second plurality of doped regions, the first and second pluralities of doped regions arranged in a first alternating pattern;
- and
- an array of metalized pads fabricated on a surface of the substrate, the array including a first plurality of pads and a second plurality of pads, with the first and second pluralities of pads arranged in a second alternating pattern;
- wherein the first plurality of pads are electrically connected to the first plurality of doped regions and the second plurality of pads are electrically connected to the second plurality of doped regions, and wherein the first plurality of pads are connected to a first terminal of the voltage regulator and the second plurality of pads are connected to a second terminal in the voltage regulator.
A power switch for a voltage regulator having an input terminal and an output terminal, comprising:
- a PMOS switch fabricated on a chip with a first alternating pattern of source pads and drain pads;
- an NMOS switch fabricated on the chip with a second alternating pattern of source pads and drain pads;
- and
- a substrate having a first signal layer with a first electrode to electrically couple the drain pads of the PMOS and NMOS switches to an intermediate terminal, a second electrode to electrically couple the source pads of the PMOS switch to the input terminal, a third electrode to electrically couple the source pads of the NMOS switch to ground.
A power switch for a voltage regulator, comprising:
- a chip having an array of pads formed thereon, each pad connected to a plurality of doped regions to create a distributed array of transistors;
- and
- a substrate having a signal layer formed thereon, the signal layer having a first electrode and a second electrode, the first electrode having a body and a plurality of fingers that extend from the body toward the second electrode, the second electrode having a body and plurality of fingers that extend toward the first electrode, wherein the fingers of the first electrode and are interdigited with the fingers of the second electrode and each finger overlies and is electrically coupled to a row of pads on the chip.
Dependencies are inferred from the claim text.