Scalable mesh architecture with reconfigurable paths for an on-chip data transfer network incorporating a network configuration manager

A dynamically reconfigurable communications network on a computer chip, comprising:

• a plurality of communications links for transmitting data;
• a plurality of communication nodes, wherein each of said communication nodes are directly connected to one or more other communication nodes through respective ones of said plurality of communications links, wherein each of said communication nodes are operable to communicate data over the plurality of communications links;
• a plurality of modules, wherein each of said plurality of modules is coupled to at least one of said plurality of communication nodes, wherein said plurality of modules are operable to communicate with each other through data transmissions via said communication nodes over a multiplicity of routes;
• a network configuration manager comprised on said computer chip, wherein said network configuration manager is coupled to said plurality of communications nodes for dynamically reconfiguring said multiplicity of routes formed by said plurality of communications links and said plurality of communication nodes, wherein said network configuration manager is operable to control said plurality of communications nodes to selectively enable and disable one or more of said communications links to selectively provide communication between selected ones of said plurality of modules along one or more of said multiplicity of routes wherein each of said plurality of communication nodes includes respective configuration logic for dynamically reconfiguring said multiplicity of routes as controlled by said network configuration manager.