Methods and apparatus for design rule checking
AssigneePhilips Electronics North America Corporation
InventorsHarold J. Levy, Subhas Bothra, David C. Chapman
Life of this patent
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Abstract
Disclosed is a method for checking integrated circuit layout design files. The method includes identifying a via geometry that is laid out on a via mask file. Identifying a metallization geometry that is laid out on a metallization mask file. Shifting the via geometry in a first orientation to produce a first shifted via geometry. Performing a logical AND between the first shifted via geometry and the metallization geometry. The method further includes determining whether the logical AND produces a value indicative of a sufficient overlap between the identified metallization geometry and the first shifted via geometry.
Claims22
A method for checking integrated circuit layout design files, comprising the acts of:
- identifying a via geometry that is laid out on a via mask file;
- identifying a metallization line geometry that is laid out on a metallization mask file;
- shifting the via geometry in a first orientation to produce a first shifted via geometry such that the size of the first shifted via geometry remains the same as the via geometry;
- performing a logical AND between the shifted via geometry and the metallization line geometry to produce an overlap area between the first shifted via geometry and the metallization line geometry along the first orientation;
- and
- determining whether the overlap area along the first orientation is at least about 50 percent of the first shifted via geometry.
An apparatus for checking integrated circuit layout design files, comprising:
- means for identifying a via geometry that is laid out on a via mask file;
- means for identifying a metallization geometry that is laid out on a metallization mask file;
- means for shifting the via geometry in a first orientation to produce a first shifted via geometry such that the size of the first shifted via geometry remains the same as the via geometry;
- means for performing a logical AND between the first shifted via geometry and the metallization geometry to produce an overlap area between the first shifted via geometry and the metallization line geometry along the first orientation;
- and
- means for determining whether the overlap area along the first orientation is at least about 50 percent of the first shifted via geometry, wherein the overlap of at least about 50 percent is configured to produce a via resistance is less than a maximum via resistance.
A computer readable media containing program instructions for checking integrated circuit layout design files, the computer readable media comprising:
- program instructions for identifying a via geometry that is laid out on a via mask file;
- program instructions for identifying a metallization geometry that is laid out on a metallization mask file;
- program instructions for shifting the via geometry in a first orientation to produce a first shifted via geometry such that the size of the first shifted via geometry remains the same as the via geometry;
- program instructions for performing a logical AND between the first shifted via geometry and the metallization geometry to produce an overlap area between the first shifted via geometry and the metallization line geometry alone the first orientation;
- and
- program instructions for determining whether the overlap area along the first orientation is at least about 50 percent of the first shifted via geometry, wherein the overlap of the at least 50 percent is configured to produce a via resistance that is less than a maximum via resistance.
A method for checking integrated circuit layout design files, comprising the acts of:
- identifying a via geometry that is laid out on a via mask file;
- identifying a metallization line geometry that is laid out on a metallization mask file;
- shifting the via geometry in a first orientation to produce a first shifted via geometry such that the size of the first shifted via geometry remains the same as the via geometry;
- producing an overlap area between the first shifted via geometry and the metallization line geometry along the first orientation;
- and
- determining whether the overlap area along the first orientation is at least about 50 percent of the first shifted via geometry.
A method for checking integrated circuit layout design files, comprising the acts of:
- identifying a via geometry that is laid out on a via mask file;
- identifying a metallization line geometry that is laid out on a metallization mask file;
- shifting the via geometry in a first orientation to produce a first shifted via geometry such that the size of the first shifted via geometry remains the same as the via geometry;
- producing an overlap area between the first shifted via geometry and the metallization line geometry along the first orientation;
- and
- determining whether the overlap area along the first orientation is sufficient to produce a via resistance that is at least less than a maximum via resistance.
Dependencies are inferred from the claim text.